DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed July 2, 2024.
Claims 1-20 are pending. Claims 1 and 11 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on July 2, 2024. This IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-9, 11, 14-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mun et al. (U.S. 2022/0319608; hereinafter “Mun”).
Regarding independent claim 1, Mun discloses an erase method for a memory device (see Abstract), comprising:
providing a memory block (Fig. 3), wherein the memory block comprises a plurality of memory cell strings (Fig. 3: CSTRs), the plurality of the memory cell strings including a plurality of string selection transistors (Fig. 3: DSTs), a plurality of first-part memory cells (Fig. 3: MC5-MC8), a plurality of dummy cells (Fig. 3: DMC1-DMC2), a plurality of second-part memory cells (Fig. 3: MC1-MC4), and a plurality of ground selection transistors (Fig. 3: SST1-SST2), wherein each of the plurality of the string selection transistors (Fig. 3: DSTs), each of the plurality of the first-part memory cells (Fig. 3: MC5-MC8), each of the plurality of the dummy cells (Fig. 3: DMC1-DMC2), each of the plurality of the second-part memory cells (Fig. 3: MC1-MC4), and each of the plurality of the ground selection transistors (Fig. 3: SST1-SST2) are connected in series to construct each memory cell string (Fig. 3: CSTRs), each of the plurality of the dummy cells (Fig. 3: DMC1-DMC2) are disposed between one of the plurality of the first-part memory cells (Fig. 3: MC5-MC8) and one of the plurality of the second-part memory cells (Fig. 3: MC1-MC4), wherein the first-part memory cells on each memory string connected to a plurality of first word lines respectively are constructed as a plurality of first pages (Fig. 3: rows of memory cells connected to WL5-WL8), and the second-part memory cells on each memory string connected to a plurality of second word lines are constructed as a plurality of second pages (Fig. 3: rows of memory cells connected to WL1-WL4); and
performing a program operation to one of the plurality of the first pages as a selected first page (“program operation,” see page 3, par. 0041 and page 7, par. 0085);
performing the program operation to one of the plurality of the second pages as a selected second page (“program operation,” see page 3, par. 0041 and page 7, par. 0085);
performing a gate induced drain leakage (GIDL) erasing operation to the plurality of the first pages (Fig. 5: Sub-block2 (Erase target), see also page 2, par. 0009);
inhibiting the plurality of the second pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the first pages (Fig. 5: Sub-block1 (Not erase target); DWL1-DWL2 (First and second erase prevention voltage));
performing the GIDL erasing operation to the plurality of the second pages (Fig. 7: Sub-block1 (Erase target), see also page 2, par. 0009); and
inhibiting the plurality of the first pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the second pages (Fig. 7: Sub-block2 (Not erase target); DWL1-DWL2 (First and second erase prevention voltage)).
Regarding claim 4, Mun discloses wherein the dummy cells (Fig. 3: DMCs) on each memory string (Fig. 3: CSTRs) are connected to a dummy word line (Fig. 3: DWLs),
the plurality of the string selection transistors (Fig. 3: DSTs) are connected to a string selection line (Fig. 3: DSLs),
the plurality of the ground selection transistors (Fig. 3: SSTs) are connected to a ground selection line (Fig. 3: SSLs),
each memory cell string (Fig. 3: CSTRs) is coupled to a corresponding bit line (Fig. 3: BLs) through a corresponding string selection transistor (Fig. 3: DSTs), and
each memory cell string (Fig. 3: CSTRs) is coupled to a common source line (Fig. 3: CSL) through a corresponding ground selection transistor (Fig. 3: SSTs).
Regarding claim 5, Mun discloses performing the GIDL erasing operation to the plurality of the first pages comprising:
applying an erase voltage to bit lines (see page 4, par. 0046);
applying a string selection line erase voltage to the string selection line (Fig. 5: VDSL), wherein a voltage difference between the erase voltage and the string selection line erase voltage is less than or equal to a predetermined voltage difference (Fig. 5: voltage applied to BL minus VDSL); and
applying a word line erase voltage to the first word lines (Fig. 5: Erase Allowable Voltage).
Regarding claim 7, Mun discloses performing the GIDL erasing operation to the plurality of the second pages comprising:
applying an erase voltage to the common source line (see page 10, par. 0110);
applying a ground selection line erase voltage to the ground selection line (Fig. 7: VSSL), wherein a voltage difference between the erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference (Fig. 7: voltage applied to CSL minus VSSL); and
applying a word line erase voltage to the second word lines (Fig. 7: Erase Allowable Voltage).
Regarding claim 8, Mun discloses inhibiting the second pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the first pages (Fig. 5: Floating WL1-WL4 and applying erase prevention voltage to DWLs) comprising:
applying an erase voltage to the dummy word line (Fig. 5: Erase Prevention Voltage), the plurality of the second word lines (Fig. 5: VWL1-4), the ground selection line (Fig. 5: VSSL) and the common source line (see page 8, par. 0091).
Regarding claim 9, Mun discloses inhibiting the plurality of the first pages (Fig. 7: floating WL5-WL8) and the dummy cells (Fig. 7: first and second erase prevention voltage to DWL1-2) of each memory cell string while the GIDL erasing operation are performed to the plurality of the second pages (Fig. 7: Sub-block 1 (erase target)) comprising:
applying the erase voltage to the dummy word line (Fig. 7: first and second erase prevention voltage), the plurality of the first word lines (Fig. 7: VWL5-VWL8), the string selection line (Fig. 7: VDSL1-2), and bit lines (Fig. 7: voltage applied to BL) while the GIDL erasing operation are performed to the plurality of the second pages (Fig. 7: sub-block 1 (Erase target)).
Regarding independent claim 11, Mun discloses a memory device (see Abstract), comprising:
providing a memory block (Fig. 3), wherein the memory block comprises a plurality of memory cell strings (Fig. 3: CSTRs), the plurality of the memory cell strings including a plurality of string selection transistors (Fig. 3: DSTs), a plurality of first-part memory cells (Fig. 3: MC5-MC8), a plurality of dummy cells (Fig. 3: DMC1-DMC2), a plurality of second-part memory cells (Fig. 3: MC1-MC4), and a plurality of ground selection transistors (Fig. 3: SST1-SST2), wherein each of the plurality of the string selection transistors (Fig. 3: DSTs), each of the plurality of the first-part memory cells (Fig. 3: MC5-MC8), each of the plurality of the dummy cells (Fig. 3: DMC1-DMC2), each of the plurality of the second-part memory cells (Fig. 3: MC1-MC4), and each of the plurality of the ground selection transistors (Fig. 3: SST1-SST2) are connected in series to construct each memory cell string (Fig. 3: CSTRs), each of the plurality of the dummy cells (Fig. 3: DMC1-DMC2) are disposed between one of the plurality of the first-part memory cells (Fig. 3: MC5-MC8) and one of the plurality of the second-part memory cells (Fig. 3: MC1-MC4), wherein the first-part memory cells on each memory string connected to a plurality of first word lines respectively are constructed as a plurality of first pages (Fig. 3: rows of memory cells connected to WL5-WL8), and the second-part memory cells on each memory string connected to a plurality of second word lines are constructed as a plurality of second pages (Fig. 3: rows of memory cells connected to WL1-WL4);
a memory controller (Fig. 2: 156), coupled to the memory block to:
performing a program operation to one of the plurality of the first pages as a selected first page (“program operation,” see page 3, par. 0041 and page 7, par. 0085);
performing the program operation to one of the plurality of the second pages as a selected second page (“program operation,” see page 3, par. 0041 and page 7, par. 0085);
performing a gate induced drain leakage (GIDL) erasing operation to the plurality of the first pages (Fig. 5: Sub-block2 (Erase target), see also page 2, par. 0009);
inhibiting the plurality of the second pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the first pages (Fig. 5: Sub-block1 (Not erase target); DWL1-DWL2 (First and second erase prevention voltage));
performing the GIDL erasing operation to the plurality of the second pages (Fig. 7: Sub-block1 (Erase target), see also page 2, par. 0009); and
inhibiting the plurality of the first pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the second pages (Fig. 7: Sub-block2 (Not erase target); DWL1-DWL2 (First and second erase prevention voltage)).
Regarding claim 14, Mun discloses wherein the dummy cells (Fig. 3: DMCs) on each memory string (Fig. 3: CSTRs) are connected to a dummy word line (Fig. 3: DWLs),
the plurality of the string selection transistors (Fig. 3: DSTs) are connected to a string selection line (Fig. 3: DSLs),
the plurality of the ground selection transistors (Fig. 3: SSTs) are connected to a ground selection line (Fig. 3: SSLs),
each memory cell string (Fig. 3: CSTRs) is coupled to a corresponding bit line (Fig. 3: BLs) through a corresponding string selection transistor (Fig. 3: DSTs), and
each memory cell string (Fig. 3: CSTRs) is coupled to a common source line (Fig. 3: CSL) through a corresponding ground selection transistor (Fig. 3: SSTs).
Regarding claim 15, Mun discloses the memory controller performs the GIDL erasing operation to the plurality of the first pages comprising:
applying an erase voltage to bit lines (see page 4, par. 0046);
applying a string selection line erase voltage to the string selection line (Fig. 5: VDSL), wherein a voltage difference between the erase voltage and the string selection line erase voltage is less than or equal to a predetermined voltage difference (Fig. 5: voltage applied to BL minus VDSL); and
applying a word line erase voltage to the first word lines (Fig. 5: Erase Allowable Voltage).
Regarding claim 17, Mun discloses wherein the memory controller performs the GIDL erasing operation to the plurality of the second pages comprising:
applying an erase voltage to the common source line (see page 10, par. 0110);
applying a ground selection line erase voltage to the ground selection line (Fig. 7: VSSL), wherein a voltage difference between the erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference (Fig. 7: voltage applied to CSL minus VSSL); and
applying a word line erase voltage to the second word lines (Fig. 7: Erase Allowable Voltage).
Regarding claim 18, Mun discloses wherein the memory controller inhibits the second pages and the dummy cells of each memory cell string while the GIDL erasing operation are performed to the plurality of the first pages (Fig. 5: Floating WL1-WL4 and applying erase prevention voltage to DWLs) comprising:
applying an erase voltage to the dummy word line (Fig. 5: Erase Prevention Voltage), the plurality of the second word lines (Fig. 5: VWL1-4), the ground selection line (Fig. 5: VSSL) and the common source line (see page 8, par. 0091).
Regarding claim 19, Mun discloses wherein the memory controller inhibits the plurality of the first pages (Fig. 7: floating WL5-WL8) and the dummy cells (Fig. 7: first and second erase prevention voltage to DWL1-2) of each memory cell string while the GIDL erasing operation are performed to the plurality of the second pages (Fig. 7: Sub-block 1 (erase target)) comprising:
applying the erase voltage to the dummy word line (Fig. 7: first and second erase prevention voltage), the plurality of the first word lines (Fig. 7: VWL5-VWL8), the string selection line (Fig. 7: VDSL1-2), and bit lines (Fig. 7: voltage applied to BL) while the GIDL erasing operation are performed to the plurality of the second pages (Fig. 7: sub-block 1 (Erase target)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Mun et al. (U.S. 2022/0319608; hereinafter “Mun”) in view of Otterstedt et al. (U.S. 2014/0126306; hereinafter “Otterstedt”).
Regarding claim 2, Mun discloses the limitations with respect to claim 1.
However, Mun is silent with respect to the step of correspondingly generating physically unclonable function (PUF) data according to the plurality of the first memory cells and the plurality of the second memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of the memory cell strings.
Otterstedt teaches generating physically unclonable function (PUF) data according to the plurality of the first memory cells and the plurality of the second memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of the memory cell strings (see page 6, par. 0098-0100).
Since Otterstedt and Mun are from the same field of endeavor, the teachings described by Otterstedt would have been recognized in the pertinent art of Mun.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Otterstedt with the teachings of Mun for the purpose of reduce the amount of specially designed and implemented PUF, see Otterstedt’s page 1, par. 0004.
Regarding claim 3, Mun discloses the limitations with respect to claim 1.
However, Mun is silent with respect to performing a read operation to the selected first page to obtain a first PUF data, and performing the read operation to the selected second page to obtain a second PUF data.
Otterstedt teaches performing a read operation to the selected first page to obtain a first PUF data, and performing the read operation to the selected second page to obtain a second PUF data (see page 7, par. 0108 and pages 8-9, par. 0124-0125).
Since Otterstedt and Mun are from the same field of endeavor, the teachings described by Otterstedt would have been recognized in the pertinent art of Mun.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Otterstedt with the teachings of Mun for the purpose of reduce the amount of specially designed and implemented PUF, see Otterstedt’s page 1, par. 0004.
Regarding claim 12, Mun discloses the limitations with respect to claim 11.
However, Mun is silent with respect to correspondingly generating physically unclonable function (PUF) data according to the plurality of the first memory cells and the plurality of the second memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of the memory cell strings.
Otterstedt teaches generating physically unclonable function (PUF) data according to the plurality of the first memory cells and the plurality of the second memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of the memory cell strings (see page 6, par. 0098-0100).
Since Otterstedt and Mun are from the same field of endeavor, the teachings described by Otterstedt would have been recognized in the pertinent art of Mun.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Otterstedt with the teachings of Mun for the purpose of reduce the amount of specially designed and implemented PUF, see Otterstedt’s page 1, par. 0004.
Regarding claim 13, Mun discloses the limitations with respect to claim 11.
However, Mun is silent with respect to performing a read operation to the selected first page to obtain a first PUF data, and performing the read operation to the selected second page to obtain a second PUF data.
Otterstedt teaches performing a read operation to the selected first page to obtain a first PUF data, and performing the read operation to the selected second page to obtain a second PUF data (see page 7, par. 0108 and pages 8-9, par. 0124-0125).
Since Otterstedt and Mun are from the same field of endeavor, the teachings described by Otterstedt would have been recognized in the pertinent art of Mun.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Otterstedt with the teachings of Mun for the purpose of reduce the amount of specially designed and implemented PUF, see Otterstedt’s page 1, par. 0004.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mun et al. (U.S. 2022/0319608; hereinafter “Mun”) in view of Lee (U.S. 2016/0141043).
Regarding claim 6, Mun discloses the limitations with respect to claim 5.
However, Mun is silent with respect to wherein the predetermined voltage difference ranges from 0 volt to 5 volts.
Similar to Mun, Lee teaches GIDL erasing operation (see page 7, par. 0081) applying an erase voltage to bit lines (see page 7, Table 6: Verase to BL) and applying a string selection line erase voltage to the string selection line (see page 7, Table 6: Vdsl to DSL).
Furthermore, Lee teaches a voltage difference between the erase voltage and the string selection line erase voltage is less than or equal to a predetermined voltage difference, wherein the predetermined voltage difference ranges from 0 volt to 5 volts (“Vdsl lower than the erase voltage Verase by about 5V,” see page 7, par. 0086).
Since Lee and Mun are from the same field of endeavor, the teachings described by Lee would have been recognized in the pertinent art of Mun.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lee with the teachings of Mun for the purpose of improve lifetime and electrical characteristics of the semiconductor devices, see Lee’s page 8, par. 0098.
Regarding claim 16, Mun discloses the limitations with respect to claim 15.
However, Mun is silent with respect to wherein the predetermined voltage difference ranges from 0 volt to 5 volts.
Similar to Mun, Lee teaches GIDL erasing operation (see page 7, par. 0081) applying an erase voltage to bit lines (see page 7, Table 6: Verase to BL) and applying a string selection line erase voltage to the string selection line (see page 7, Table 6: Vdsl to DSL).
Furthermore, Lee teaches a voltage difference between the erase voltage and the string selection line erase voltage is less than or equal to a predetermined voltage difference, wherein the predetermined voltage difference ranges from 0 volt to 5 volts (“Vdsl lower than the erase voltage Verase by about 5V,” see page 7, par. 0086).
Since Lee and Mun are from the same field of endeavor, the teachings described by Lee would have been recognized in the pertinent art of Mun.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lee with the teachings of Mun for the purpose of improve lifetime and electrical characteristics of the semiconductor devices, see Lee’s page 8, par. 0098.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited step after the GIDL operation to the plurality of the first pages and the GIDL operation to the plurality of the second pages, all the first memory cells in a specific memory cell string are the type-1 erase bit or the type-2 erase bit, all the second memory cells in the specific memory cell string are the type-1 erase bit or the type-2 erase bit, and an erase bit type of the first memory cells and an erase bit type of the second memory cells has 0.5 inter-hamming distance.
With respect to claim 20, there is no teaching or suggestion in the prior art of record to provide the recited step after the GIDL operation to the plurality of the first pages and the GIDL operation to the plurality of the second pages, all the first memory cells in a specific memory cell string are the type-1 erase bit or the type-2 erase bit, all the second memory cells in the specific memory cell string are the type-1 erase bit or the type-2 erase bit, and an erase bit type of the first memory cells and an erase bit type of the second memory cells has 0.5 inter-hamming distance.
Conclusion
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825