Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/2/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
MPEP 2113: Product-by-Process Claims
Initially, and with respect to claim 12, note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process step “wherein an interconnect is formed on the conductive line by removing the shoulders of the via, so that the width of the interconnect via is aligned to the width of the conductive line and coplanar with the planar surface of the second dielectric material” this is considered an intermediate method step that does not affect the structure of the final device (i.e., “width”) so long as the final structure reasonably appears to be identical.
Claims 12-15, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Siew (US 20170033004 A1).
Regarding independent claim 12, Siew discloses an interconnect via (Fig. 9C: 142) for connecting a lower electrically conductive line (121/123) in a first level of a multi-level interconnect structure (WS) to an upper electrically conductive line (323) in a second level (300) overlying the first level, the interconnect via comprising:
a substrate (100) having an upper surface formed of a dielectric material ([0040]:” may further include an insulating layer”) with electrical conductors or contacts ([0040]: “may include an integrated circuit”) embedded in the dielectric material ([0040]: “covered with the insulating layer”);
a layer of a first conductive material (121/123, which is initially Fig. 1B: layer 102/104; [0050]: “metal interconnection”) and a dielectric layer (125/127, which is initially Fig. 1B: layer 106/108) formed of a first dielectric material ([0050]: “first insulating pattern”), on the layer of the first conductive material;
a conductive via (142) embedded in the dielectric layer ([0062]: “in the first insulating patterns”), wherein the upper surface of the via is coplanar with the upper surface of the dielectric layer (See annotated figure for dashed reference line A), the upper surfaces forming a planarized surface (“planarized” at the “coplanar” surfaces at the dashed reference line A);
a second dielectric material (135, which is initially Fig. 4C: layer 133) formed as to produce a planar surface (“planar surface” at dashed reference line A); and
a conductive line (121/123), wherein an interconnect via (142. Note: this via is cited twice as 142, consistent with Applicant’s disclosure: Figs. 5-6: via 6/10 showing the same via cited twice) is formed on the conductive line by removing the shoulders of the via (MPEP 2113: this Product-by-Process limitation is not disclosed in the cited prior art), so that the width of the interconnect via (Width A, See annotated figure) is aligned to the width of the conductive line (Width B, See annotated figure) and coplanar with the planar surface of the second dielectric material (“coplanar” at the dashed reference line A).
Illustrated below is a marked and annotated figure of Fig. 9C of Siew.
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Regarding claim 13, Siew discloses the interconnect via according to claim 12 (Fig. 9C), wherein the second dielectric material is deposited in such a manner that airgaps (AG) are created between adjacent conductive lines.
Regarding claim 14, Siew discloses the interconnect via according to claim 12 (Fig. 9C), further comprising:
an airgap (AG) formed on each side of the conductive line on top of which the interconnect via is formed (left and right “side”), and wherein the two airgaps have a top portion that overlaps (horizontally “overlaps”) a lower portion of the height of the interconnect via.
Regarding claim 15, Siew discloses the interconnect via according to claim 14, wherein the two airgaps are directly adjacent to the interconnect via (horizontally “directly adjacent”. Note: “directly adjacent” is interpreted here consistent with the directional arrangement of Applicant’s disclosure: Fig. 12, which includes portions of intervening dielectric 11).
Regarding claim 19, Siew discloses the interconnect via according to claim 12 (Fig. 9C), wherein the first and second conductive material are chosen from the group consisting of Ru, W, and Mo (102 is [0043]: “tungsten nitride”; 140/142 is [0064]: “may include ruthenium”).
Regarding claim 20, Siew discloses the interconnect via according to claim 12 (Fig. 9C), wherein the first and second dielectric material is SiO2 or a low-K material (108/127 is [0046]: “a-SiOC”; 133/135 is [0056]: “a-SiOC”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Siew as applied to claim 14 above, and further in view of Xu (US 20240243037 A1).
Regarding claim 16, Siew discloses the interconnect via according to claim 14 (Fig. 9C), however fails to teach specific height for the airgaps or via, and thus cannot be relied upon to anticipate the claimed feature “wherein the height of the top portion of the two airgaps is at least 50% of the height of the interconnect via” according to MPEP 2125 (II). Nevertheless, this claimed feature is not patentably distinct from the prior art according to MPEP M144.04 (IV)(A): Gardner, and is reasonably suggested by Siew in accord with MPEP 2125 (I).
Xu discloses wherein the height of the top portion of the two airgaps (Fig. 2: 150, height H1) is at least 50% ([0037]: “up to approximately 90%” overlaps the claimed range) of the height of the interconnect via (110, height H2). Xu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate this difference in size/proportion in that it would enable reducing parasitic capacitance for the via ([0037]: “to reduce parasitic coupling capacitance”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed height configuration because it would enable reducing parasitic capacitance for the via. MPEP 2143 (I)(G); MPEP 2144.04 (IV)(A): Gardner.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Siew as applied to claim 12 above, and further in view of Xie (US 20240321630 A1) and Chang (US 20230163071 A1).
Regarding claim 17, Siew discloses the interconnect via according to claim 12 (Fig. 9C), however fails to teach specific dimensions for the via, and thus fails to teach “wherein the interconnect via has nano-sized dimensions in three orthogonal directions”. Nevertheless, this claimed feature is not patentably distinct from the prior art according to MPEP M144.04 (IV)(A): Gardner.
Xie discloses wherein the interconnect via has nano-sized dimensions in three orthogonal directions (Note: one direction, i.e., height is relied upon here. [0065]: “thicker…thinner than the first metal layer” combined with [0063]: “approximately 20 nm to approximately 100 nm”). Incorporating these nano-sized dimensions (of Xie) with the interconnect via (of Siew) would partially arrive at the claimed size configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Xie teaches the via being formed ([0092]: “filled”) in substantially the same way as Siew ([0064]: “fill”). Therefore, the claimed dimensions would have been obvious to one of ordinary skill in the art before the effective filing date because it is a difference in size encompassed by teachings for similar vias found elsewhere in the prior art. MPEP 2144.04 (IV)(A): Gardner.
Chang discloses wherein the interconnect via has nano-sized dimensions in three orthogonal directions (Note: two direction, i.e., length and width are relied upon here. Fig. 7C: D2 and D1´; [0039]: “about 10 nm to about 100 nm” combined with [0047]: “width”). Incorporating these nano-sized dimensions (of Chang) with the interconnect via (of Siew) would partially arrive at the claimed size configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Chang teaches the via being formed ([0037]: “filling”) in substantially the same way as Siew ([0064]: “fill”). Therefore, the claimed dimensions would have been obvious to one of ordinary skill in the art before the effective filing date because it is a difference in size encompassed by teachings for similar vias found elsewhere in the prior art. MPEP 2144.04 (IV)(A): Gardner.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Siew as applied to claim 12 above, and further in view of Xie.
Regarding claim 18, Siew discloses the interconnect via according to claim 12 (Fig. 9C), however fails to teach specific dimensions for the via, and thus fails to teach “wherein the height of the interconnect via is between 10 nm and 30 nm”. Nevertheless, this claimed feature is not patentably distinct from the prior art according to MPEP M144.04 (IV)(A): Gardner.
Xie discloses wherein the height of the interconnect via is between 10 nm and 30 nm ([0065]: “thicker…thinner than the first metal layer” combined with [0063]: “approximately 20 nm to approximately 100 nm”). Incorporating this height dimension (of Xie) with the interconnect via (of Siew) would arrive at the claimed size configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Xie teaches the via being formed ([0092]: “filled”) in substantially the same way as Siew ([0064]: “fill”). Therefore, the claimed dimension would have been obvious to one of ordinary skill in the art before the effective filing date because it is a difference in size encompassed by teachings for similar vias found elsewhere in the prior art. MPEP 2144.04 (IV)(A): Gardner.
Allowable Subject Matter
Claims 1-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1-11 is the inclusion of the limitation “removing the dielectric layer and the first and second conductive material in the areas not covered by the hardmask line, thereby obtaining a conductive line, wherein an interconnect via is formed on the conductive line by removing the shoulders of the via, so that the width of the interconnect via is aligned to the width of the conductive line” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “hardmask line”, “shoulders”, and “aligned” when these features were considered in combination with all other sequences and structures required in claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
