Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed February 25th, 2026 has been entered. Claims 1 and 3-25 are pending in this applicationth, 2025 have been maintained.
Response to Arguments
Applicant's arguments filed February 25th, 2026 have been fully considered but they are not persuasive.
Applicant argues that the cited references fail to teach or suggest the amended limitations of independent claims 1, 11, 20, and 23.
Regarding independent claim 1, Applicant argues that the cited references fail to teach generating a second codeword by appending a first codeword to data to form a combined codeword before applying an error control code. However, the rejection does not rely on just one reference to teach this limitation, but a combination of Hu et al. (US 10,116,336), hereinafter Hu, in view of Moyer (US 8,918,707). Hu teaches applying an error control code to input data to generate a codeword, while Moyer teaches generating a first codeword based on address information. It would have been obvious to a person of ordinary skill in the art to append the first codeword (address-derived information) to the data before performing ECC encoding to protect both the data and the address information.
Regarding independent claim 11, Applicant argues that the references do not teach decoding a second codeword to obtain both data and a third codeword corresponding to address information. However, Spencer et al. (US 2005/0060628), hereinafter Spencer, teaches decoding a codeword using an error control code to obtain corrected data. Moyer teaches that the codeword includes information derived from both data and address information. A person of ordinary skill in the art would have recognized that decoding a codeword containing information from both data and address information, would involve processing and reconstructing error control information corresponding to both the data and address information, such as checkbits or syndromes. Therefore, the decoding operation generations both corrected data and error control information that corresponded to address information.
Regarding independent claims 20 and 23, Applicant argues that Moyer does not teach applying a function to a bank address, row address, and column addresses. However, Moyer teaches generating checkbits based on address bits associated with the data. In memory systems, address bits inherently comprise address components including bank, row, and column addresses. A person of ordinary skill in the art would have understood that the address bits taught in Moyer correspond to conventional memory address fields.
Accordingly, the rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Moyer, further in view of Spencer et al. (US 2005/0060628), hereinafter Spencer.
Regarding claim 1, Hu teaches a method, comprising: receiving data associated with a write command and an address associated with the write command (Hu, col. 3, lines 28-38, “The controller 120 is configured to receive data and instructions from the host device 156 and to send data to the host device 156. For example, the controller 120 may send data to the host device 156 via the host interface 152 and may receive data from the host device 156 via the host interface 152” through col. 4, line 1, “the controller 120 may receive user data [e.g., host data] and a request for write access to the memory 104 from the host device 156 via the host interface 152. The controller 120 is configured to send data and commands to the memory 104 and to receive data from the memory 104. For example, the controller 120 is configured to send data and a write command to cause the memory 104 to store the data to a specified address of the memory 104”); and generating a second codeword based at least in part on applying an error control code to the first codeword and the data (Hu, col. 2 lines 49-50, “The encoder 162 is configured to receive data and to generate one or more ECC codewords based on the data”).
Hu fails to teach generating a first codeword based at least in part on applying a function to the address, generating the second codeword comprises appending the first codeword to the data to generate a combined codeword, and storing the second codeword at the address.
However, Moyer, in an analogous art, teaches generating a first codeword based at least in part on applying a function to the address (Moyer, col. 1, lines 27-33, “In general, a codeword includes a set of data bits [i.e., a data field] and a set of ECC checkbits [i.e., a checkbit field]. The ECC checkbits are generated based on the content of the data field and address information associated with a location in storage of the codeword”; col. 6, lines 5-7, “the bus master may generate the one or more checkbits by exclusive ORing address bits and data bits based on a data structure [see FIG. 2]”) and generating the second codeword comprises appending the first codeword to the data to generate a combined codeword. While Hu teaches generating an ECC codeword based on input data, and Moyer teaches generating checkbits based on address and data, it would have been obvious to a person of ordinary skill in the art to append the checkbits derived from address information (equates to a first codeword), to the data before performing the ECC encoder operations. This forms a combined codeword, which then gets processed by the ECC encoder taught by Hu (Hu, col. 2, lines 49-50), to generate the second codeword.
Hu and Moyer are both considered to be analogous to the claimed invention because both are in the same field of memory systems that use error-correcting or error-detecting codewords.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Hu to incorporate the teachings of Moyer by including the functionality of generating a codeword based on applying a function to an address received during a write operation, and .
The suggestion/motivation for doing so would be that using address information to form codewords allows for additional error detection capabilities (Moyer, col. 1, lines 26-27, “utilizing address information in the formation of a codeword provides additional error detection capabilities”), as well as improve the integrity of data and allow for error detection in both the data and address information.
The combination of Hu in view Moyer, taken singly or combined, fails to teach storing the second codeword at the address.
However, Spencer, in an analogous art, teaches storing the second codeword at the address (Spencer, para. [0007], lines 6-10, “When multiple units of data are to be written to the device for an address, the multiple units of data are encoded together to generate a codeword and the generated codeword is written to the memory array in a location associated with the address”).
Hu, Moyer, and Spencer are considered to be analogous to the claimed invention because they are in the same field of memory systems that use error-correcting or error-detecting codewords.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hu, in view of Moyer to incorporate the teachings of Spencer by including the functionality of storing a codeword at an address received during a write operation.
The suggestion/motivation for doing so would be an obvious design choice to ensure the reliable retrieval of the codeword during the error correction process.
Regarding claim 4, the combination of Hu, in view of Moyer, further in view of Spencer teaches the method of claim 3, wherein receiving the write command comprises: receiving a column address associated with the data, wherein generating the first codeword comprises applying the function to the bank address, the row address, and the column address (Moyer, col. 7, lines 20-23, “The method of claim 2, further comprising: generating the one or more checkbits by exclusive ORing the data bits and address bits associated with the data bits based on a data structure”; the reference does not teach the function applied to bank, row, and column addresses specifically, however the address bits encompass physical address components).
Regarding claim 10, the combination of Hu, in view of Moyer, further in view of Spencer teaches the method of claim 1, wherein the function comprises an error control operation (Moyer, col. 1, lines 26-27, “utilizing address information in the formation of a codeword provides additional error detection capabilities”; col. 7, lines 20-23, “generating the one or more checkbits by exclusive ORing the data bits and address bits associated with the data bits based on a data structure”; the exclusive OR operation equates to an error control operation) different than the error control code (Moyer, col. 1, lines 29-32, “The ECC checkbits are generated based on the content of the data field and address information associated with a location in storage of the codeword”; the ECC checkbits represent standard ECC code generation, which is different than the exclusive OR operation).
Claim 3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Moyer, further in view of Spencer, further in view of JEDEC STANDARD Double Data Rate (DDR) SDRAM Specification (Revision of JESD79B), hereinafter JEDEC.
Regarding claim 3, the combination of Hu, in view of Moyer, further in view of Spencer teaches the method of claim 1, but fails to teach further comprising: receiving, as part of an activate command, a row address associated with the data and a bank address associated with the data, wherein receiving the write command is based at least in part on receiving the activate command.
However, JEDEC, in an analogous art, teaches further comprising: receiving, as part of an activate command, a row address associated with the data and a bank address associated with the data (JEDEC, pg. 7, para. 3, lines 4-6, "Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command"), wherein receiving the write command is based at least in part on receiving the activate command (JEDEC, pg. 19, para. 4, lines 1-3, "The ACTIVE command is used to open [or activate] a row in a particular bank for a subsequent access").
Hu, Moyer, Spencer and JEDEC are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices and error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hu, in view of Moyer, further in view of Spencer, to incorporate the teachings of JEDEC by including the functionality of using an activate command to get a row address and bank address.
The suggestion/motivation for doing so would be a predictable design choice necessary for operating industry-standard DRAM devices, allowing a memory system to perform ECC protection along with standard command sequences.
Regarding claim 5, the combination of Hu, in view of Moyer, further in view of Spencer, further in view of JEDEC teaches the method of claim 3, further comprising: storing, as part of executing the activate command, the row address at a bank associated with the bank address (JEDEC, pg. 19, para. 4, lines 1-3, "The ACTIVE command is used to open [or activate] a row in a particular bank for a subsequent access”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hu, in view of Moyer, further in view of Spencer ,to incorporate the teachings of JEDEC by including the functionality of storing the row address at a bank address, as part of executing an activate command.
The suggestion/motivation for doing so would be to enable a row of a particular bank for subsequent access (JEDEC, pg. 19, para. 4, lines 1-3, "The ACTIVE command is used to open [or activate] a row in a particular bank for a subsequent access”).
Regarding claim 6, the combination of Hu, in view of Moyer, further in view of Spencer teaches the method of claim 1, but fails to teach wherein the address comprises a bank address associated with the data, a row address associated with the data, and a column address associated with the data.
However, JEDEC teaches wherein the address comprises a bank address associated with the data, a row address associated with the data, and a column address associated with the data (JEDEC, page 31, Fig. 18 teaches a column and bank address, page 19 teaches row addresses).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hu, in view of Moyer, further in view of Spencer to incorporate the teachings of JEDEC by including the functionality of having row, column, and bank addresses associated with data.
The suggestion/motivation for doing so would be that the use of row, column, and bank addressing is a well-known design practice in memory systems to increase capacity and performance.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Moyer, further in view of Spencer, further in view of Swaminathan et al. (US 2007/0260828), hereinafter Swaminathan.
Regarding claim 7, the combination of Hu, in view of Moyer, further in view of Spencer teaches the method of claim 1, further comprising: the first codeword based at least in part on retrieving the second codeword from the address; generating a third codeword based at least in part on applying the function to the address; and incrementing the address counter based at least in part on performing an error control procedure using the first codeword and the third codeword (Moyer, col. 6, lines 10-16, “The bus master initiates storing the codeword [via a write operation] in a slave at the address. The bus master may then read the codeword from the slave and determine whether the codeword read from the slave has the one or more bit errors that were injected into the codeword”).
The combination of Hu, in view of Moyer, further in view of Spencer fails to teach identifying, as part of a background operation and based at least in part on an address counter corresponding to the address.
However, Swaminathan, in an analogous art, teaches identifying, as part of a background operation (Swaminathan, para. [0002], lines 6-10, “memory controllers usually implement a scheme called 'patrol scrubbing', wherein each data entry in the entire memory is read periodically and if it has a correctable error, it will be corrected and written back to the memory, thereby avoiding the accumulation of errors”; para. [0018], lines 1-3, “The patrol scrubber 200 may raise a patrol request, for example a patrol read request, to a memory command scheduler 210 after patrol time interval expires”; the reference do3es not explicitly teach ‘background operation’, however it teaches ‘patrol scrubbing’, which is a background maintenance operation in memory systems that utilize error correction) and based at least in part on an address counter corresponding to the address (Swaminathan, para. [0021], lines 2-5, "As depicted the patrol scrubber 200 may comprise a comparator 300, a patrol scrub logic 310, an address counter 320”; para. [0022], lines 4-8, "The address counter 320 may register the request and may transmit the request along with the current patrol address to an address storage register 330 so as to forward the same to a memory command scheduler 210"; the patrol scrub subsystem maintains an address counter that identifies the current address being verified during background scrubbing).
Hu, Moyer, Spencer and Swaminathan are considered to be analogous to the claimed invention because they are in the same field of same field of semiconductor memory devices and error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hu, in view of Moyer, further in view of Spencer to incorporate the teachings of Swaminathan by including the functionality of a identifying an address during a background operation and an address counter.
The suggestion/motivation for doing so would be to avoid the accumulation of errors (Swaminathan, para. [0002], lines 6-10, “memory controllers usually implement a scheme called 'patrol scrubbing', wherein each data entry in the entire memory is read periodically and if it has a correctable error, it will be corrected and written back to the memory, thereby avoiding the accumulation of errors”) and automate sequential ECC verification across all addresses in the memory, predictable design choice yielding improvement in error coverage and system reliability.
Regarding claim 8, the combination of Hu, in view of Moyer, further in view of Spencer, further in view of Swaminathan teaches the method of claim 7, wherein performing the error control procedure comprises: identifying an error in the first codeword; and storing an indication of the error (Moyer, col. 3, lines 4-7, “The technique includes determining whether one or more checkbits of the codeword are affected by one or more bit errors that are to be injected into the codeword”), wherein incrementing the address counter is based at least in part on storing the indication (Swaminathan, para. [0025], lines 5-9, "patrol request acknowledgement/indication may be sent to the patrol scrub logic 310, indicating completion of the request without any errors, by the memory controller data path and the patrol address counter 320 may be incremented so as facilitate raising a new patrol request").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Hu, in view of Moyer, further in view of Spencer to incorporate the teachings of Swaminathan by including the functionality of incrementing an address counter based in part on storing an indication of an error in a first codeword.
The suggestion/motivation for doing so would be so that each address can be checked for errors, the detected errors can be recorded, and then advance to the next address. This is a common reliability technique in memory controllers.
Regarding claim 9, the combination of Helmick in view of Hu, further in view of Swaminathan teaches the method of claim 7, wherein performing the error control procedure comprises: determining that the first codeword and the third codeword match; and storing the first codeword at the address based at least in part on determining that the first codeword and the third codeword match (Moyer, col. 6, lines 12-15, “The bus master may then read the codeword from the slave and determine whether the codeword read from the slave has the one or more bit errors that were injected into the codeword”; the determination of whether codeword from the slave contains one or more bit errors entails a match check).
Claims 11-17 and 20-25 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer, in view of Pline et al. (US 2005/0120265), hereinafter Pline, further in view of Spencer.
Regarding claim 11, Moyer teaches a method, comprising: generating a first codeword based at least in part on applying a function to the address (Moyer, col. 3, lines 51-56, “For example, with reference to the data structure of FIG. 2, checkbit [7] is determined by XORing data bits… with address bits…”); and performing an error control operation using the first codeword and the third codeword (Moyer, col. 4, lines 64-67 through col. 5, lines 1-5, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits. The third checkbits are coupled to an XOR gate 310, which is also coupled to an error control and status register [ECSR0] [Checkbit Invert Cntl] 312 that may be programmed to invert desired checkbits to emulate errors in one or more data bits and/or one or more address bits”).
Moyer fails to teach receiving, from a host device, a read command for data and an address associated with the data; identifying a second codeword stored in a memory array at the address; decoding the second codeword to obtain the data and a third codeword based at least in part on an error control code that covers the data and the third codeword, wherein the third codeword corresponds to address information; and transmitting the data to the host device based at least in part on performing the error control operation.
However, Pline, in an analogous art, teaches receiving, from a host device, a read command for data and an address associated with the data (Pline, Fig. 8, block 508) and transmitting the data to the host device based at least in part on performing the error control operation (Pline, Fig. 8, step 510; the storage device sends the data to the host after a read ECC operation is performed).
Moyer and Pline are both considered to be analogous to the claimed invention because both are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Moyer to incorporate the teachings of Pline by including the functionality of receiving a read command and address associated with data from a host, and transmitting the data back to the host device after performing an error control operation.
The suggestion/motivation for doing so would be because it is the standard host-to-device read command flow/process used in memory systems with error correction capabilities.
The combination of Moyer in view Pline, taken singly or combined, fails to teach identifying a second codeword stored in a memory array at the address and decoding the second codeword to obtain the data and a third codeword based at least in part on an error control code that covers the data and the third codeword, wherein the third codeword corresponds to address information.
However, Spencer, in an analogous art, teaches identifying a second codeword stored in a memory array at the address (Spencer, para. [0006], lines 6-9, “When multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array”); and decoding the second codeword to obtain the data and a third codeword based at least in part on an error control code that covers the data and the third codeword, wherein the third codeword corresponds to address information (Spencer, para. [0006], lines 9-12, “the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block”). While Spencer does not explicitly teach the limitation “decoding the second codeword to obtain the data and a third codeword based at least in part on an error control code that covers the data and the third codeword, wherein the third codeword corresponds to address information”, it does teach decoding a codeword, performing error correction on the data block associated with the codeword, and reading multiple data units from the corrected data block. A person of ordinary skill in the art would recognize that when decoding a codeword that includes address-related information (taught by Moyer), the decoding process inherently regenerates error-control information such as checkbits or syndromes that correspond to address information (equates to a third codeword).
Moyer, Pline, and Spencer are considered to be analogous to the claimed invention because they are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer in view of Pline to incorporate the teachings of Spencer by including the functionality of identifying a codeword stored in a memory array at a received address, and decoding the codeword to get data and a third codeword generated in part of an error control code.
The suggestion/motivation for doing so would be to improve the reliability of the memory system. Decoding techniques are a predictable way to recover data and determine errors during read operations.
Regarding claim 12, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 11, further comprising: identifying an address error based at least in part on comparing the first codeword and the third codeword (Moyer, col. 4, lines 64-67 through col. 5, lines 1-5, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits. The third checkbits are coupled to an XOR gate 310, which is also coupled to an error control and status register [ECSR0] [Checkbit Invert Cntl] 312 that may be programmed to invert desired checkbits to emulate errors in one or more data bits and/or one or more address bits”); and transmitting an indication of the address error to the host device based at least in part on identifying the address error (Pline, para. [0105], lines 4-10, “the read ECC coding flag is set, a 640 byte ECC encoded data sector 202 is read from storage device 24, and if the read ECC coding flag is cleared, a 512 byte original data sector 200 is read from storage device 24. At 510, host processor 26 receives the data from storage device 24 and storage device 24 signals host processor 26 to indicate that the data has been transferred”; para. [0107], lines 1-2, “the read ECC coding flag is set, a 640 byte ECC encoded data sector 202 is read from storage device 24, and if the read ECC coding flag is cleared, a 512 byte original data sector 200 is read from storage device 24. At 510, host processor 26 receives the data from storage device 24 and storage device 24 signals host processor 26 to indicate that the data has been transferred”; the read ECC coding flag equates to an indication of an error).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Helmick to incorporate the teachings of Hu by including the functionality of transmitting an address error indication to a host device.
The suggestion/motivation for doing so is that it is a predictable design choice to notify a host device of an error during error detection operations in memory.
Regarding claim 13, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 12, further comprising: storing an indication of the address error (Moyer, col. 4, lines 64-67 through col. 5, lines 1-5, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits. The third checkbits are coupled to an XOR gate 310, which is also coupled to an error control and status register [ECSR0] [Checkbit Invert Cntl] 312 that may be programmed to invert desired checkbits to emulate errors in one or more data bits and/or one or more address bits”).
Regarding claim 14, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 13, further comprising: receiving a command to retrieve the indication of the address error, wherein transmitting the indication of the address error to the host device is further based at least in part on receiving the command to retrieve the indication of the address error (Pline, para. [0104], lines 10-12, “Host processor 26 provides a read command with the read ECC coding flag and a read start address to storage device 24 at 508”).
Regarding claim 15, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 12, further comprising: receiving, based at least in part on identifying the address error, a command to disable one or more memory cells associated with the address; and disabling the one or more memory cells based at least in part on receiving the command to disable the one or more memory cells (Pline, claim 1 teaches “…a sparing system configured to replace defective memory sections of a memory device with replacement memory sections of the memory device”).
Regarding claim 16, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 11, wherein identifying the second codeword comprises: retrieving the second codeword from the address (Spencer, Fig. 2B, step 254); and applying an error control code to the second codeword based at least in part on retrieving the second codeword (Spencer, Fig. 2B, step 256).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer, in view of Pline to incorporate the teachings of Spencer by including the functionality of retrieving a second codeword from an address and applying an error control code to the codeword.
The suggestion/motivation for doing so would be to determine if the second codeword contains errors (Spencer, para. [0019], lines 16-21, “The ECC module determines if the block of data in the codeword contains any errors, and corrects the errors, if necessary. This operation is also referred to here as ‘decoding.’ The result of this decoding operation is referred to here as ‘a corrected block of data,’ ‘corrected data block,’ or ‘corrected data’”).
Regarding claim 17, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 16, wherein applying the error control code comprises: identifying an error in the third codeword; and correcting the error, wherein performing the error control operation is based at least in part on correcting the error (Spencer, para. [0019], lines 12-22, “Examples of error codes include Hamming codes, Reed-Solomon codes, binary Golay codes, binary Goppa codes, or BCH codes. When a unit of data is read from assisted memory 120, a codeword that contains the desired data is fetched from the memory array 104. The ECC module 108 determines if the block of data in the codeword contains any errors, and corrects the errors, if necessary. This operation is also referred to here as ‘decoding.’ The result of this decoding operation is referred to here as ‘a corrected block of data, ‘corrected data block,’ or ‘corrected data.’ The unit of data is then retrieved from the corrected block of data”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer, in view of Pline to incorporate the teachings of Spencer by including the functionality of identifying errors and correcting the error via an error control operation.
The suggestion/motivation for doing so would be that these steps embody the error correction process: identifying errors in data and then performing an operation/operations to correct the errors.
Regarding claim 20, Moyer teaches a method, comprising: generating a first codeword based at least in part on applying a function to a bank address associated with the data, a row address associated with the data, and a column address associated with the data (Moyer, col. 3, lines 51-56, “For example, with reference to the data structure of FIG. 2, checkbit [7] is determined by XORing data bits… with address bits…”; memory controllers split addresses into bank, row, and column fields, therefore the address bits equates to bank, row, and column addresses); generating a third codeword based at least in part on applying a second function the first codeword and the second codeword (Moyer, col. 4, lines 64-67 through col. 5, lines 1-5, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits. The third checkbits are coupled to an XOR gate 310, which is also coupled to an error control and status register [ECSR0] [Checkbit Invert Cntl] 312 that may be programmed to invert desired checkbits to emulate errors in one or more data bits and/or one or more address bits”); and storing the data and the third codeword in a memory array at the address (Moyer, col. 5, lines 5-12, “Outputs of XOR gate 310 provide final checkbits that are stored at an address [Addr] specified on the bypassed address line. The final checkbits are associated with data [Data] on the bypassed data lines and are stored at the address [Addr] in storage array 304 responsive to control [Ctrl] signals provided by control logic [e.g., a bus interface unit (BIU)] of the CPU102”).
Moyer fails to teach receiving data associated with a write command and an address associated with the write command and generating a second codeword based at least in part on applying an error control code to the data.
However, Pline, in an analogous art, teaches receiving data associated with a write command and an address associated with the write command (Pline, Fig. 7, block 414).
Moyer and Pline are both considered to be analogous to the claimed invention because both are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Moyer to incorporate the teachings of Pline by including the functionality of receiving a write command and address associated with data from a host.
The suggestion/motivation for doing so would be because it is the standard host-to-device write command flow/process to receive an address with a write command, allowing for corrected data to be written to the appropriate memory location.
The combination of Moyer, in view of Pline, taken singly or combined, fails to teach generating a second codeword based at least in part on applying an error control code to the data.
However, Spencer, in an analogous art, teaches generating a second codeword based at least in part on applying an error control code to the data (Spencer, para. [0019], lines 4-9, “When data is written to the assisted memory 102, the ECC module 108 ‘encodes’ the fixed block of data by adding parity bits to the block of data [referred to here as an "error correction code" or "parity block"]. The result is a "codeword" that includes the original block of data and the parity bits”).
Moyer, Pline, and Spencer are considered to be analogous to the claimed invention because they are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer in view of Pline to incorporate the teachings of Spencer by including the functionality of generating a codeword based on applying an error control code to data.
The suggestion/motivation for doing so would be to improve the reliability of the data in the memory system.
Regarding claim 21, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 20, wherein the second function comprises an Exclusive-OR operation (Moyer, col. 3, lines 51-56, “For example, with reference to the data structure of FIG. 2, checkbit [7] is determined by XORing data bits… with address bits…”).
Regarding claim 22, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 20, wherein the first codeword and the second codeword each comprise a same quantity of bits (Moyer, col. 4, lines 64-67 through col. 5, line 1, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits”). The reference teaches an XOR operation being applied to input checkbits, which implies that the checkbits (the codewords) are of the same length since corresponding bits are compared individually in XOR operations.
Regarding claim 23, Moyer teaches a method, comprising: generating a first codeword based at least in part on applying a function to a bank address associated with the data, a row address associated with the data, and a column address associated with the data (Moyer, col. 3, lines 51-56, “For example, with reference to the data structure of FIG. 2, checkbit [7] is determined by XORing data bits… with address bits…”; memory controllers split addresses into bank, row, and column fields, therefore the address bits equates to bank, row, and column addresses); identifying a third codeword stored in a memory array at the address (Moyer, col. 5, lines 5-10, “Outputs of XOR gate 310 provide final checkbits that are stored at an address [Addr] specified on the bypassed address line. The final checkbits are associated with data [Data] on the bypassed data lines and are stored at the address [Addr] in storage array 304”); and generating an error control code based at least in part on applying a second function to the first codeword and the third codeword (Moyer, col. 4, lines 64-67 through col. 5, lines 1-5, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits. The third checkbits are coupled to an XOR gate 310, which is also coupled to an error control and status register [ECSR0] [Checkbit Invert Cntl] 312 that may be programmed to invert desired checkbits to emulate errors in one or more data bits and/or one or more address bits”).
Moyer fails to teach receiving, from a host device, a read command for data and an address associated with the data; identifying a second codeword stored in a memory array at the address; decoding the second codeword to obtain the data based at least in part on the error control code; and transmitting the data to the host device based at least in part on decoding the second codeword.
However, Pline, in an analogous art, teaches receiving, from a host device, a read command for data and an address associated with the data (Pline, Fig. 8, block 508) and transmitting the data to a host device based at least in part on decoding the second codeword (Pline, para. [0042], lines 5-10, “In the event the received data is ECC encoded data, host processor 26 executes ECC decoder 46 to decode the ECC encoded data. The ECC encoded data is decoded and corrected to provide data originally received for storage in storage device 24, referred to herein as original data”).
Moyer and Pline are both considered to be analogous to the claimed invention because both are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Moyer to incorporate the teachings of Pline by including the functionality of receiving a read command and address associated with data from a host, and transmitting the data back to the host device after performing a decoding operation.
The suggestion/motivation for doing so would be because it is the standard host-to-device read command flow/process used in memory systems with error correction capabilities.
The combination of Moyer in view Pline, taken singly or combined, fails to teach identifying a second codeword stored in a memory array at the address and decoding the second codeword to obtain the data based at least in part on the error control code.
However, Spencer, in an analogous art, teaches identifying a second codeword stored in a memory array at the address (Spencer, para. [0019], lines 10-12, “The codeword is stored in the memory array 104 at a location associated with a supplied address”) and decoding the second codeword to obtain the data based at least in part on the error control code (Spencer, para. [0006], lines 9-12, “the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block”).
Moyer, Pline, and Spencer are considered to be analogous to the claimed invention because they are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer in view of Pline to incorporate the teachings of Spencer by including the functionality of identifying a codeword stored in a memory array at a received address, and decoding the codeword to get data based in part of an error control code.
The suggestion/motivation for doing so would be to improve the reliability of the memory system. Decoding techniques are a predictable way to recover data and determine errors during read operations.
Regarding claim 24, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 23, further comprising: identifying an address error based at least in part on applying the second function (Moyer, col. 4, lines 64-67 through col. 5, lines 1-5, “The logic 302 generates first checkbits for an address portion of a codeword and the logic 306 generates second checkbits for a data portion of the codeword. Outputs of the logic 302 and 306 are exclusive ORed (by XOR gate 308) to provide third checkbits. The third checkbits are coupled to an XOR gate 310, which is also coupled to an error control and status register [ECSR0] [Checkbit Invert Cntl] 312 that may be programmed to invert desired checkbits to emulate errors in one or more data bits and/or one or more address bits”); and transmitting an indication of the address error to the host device based at least in part on identifying the address error (Pline, para. [0105], lines 4-10, “the read ECC coding flag is set, a 640 byte ECC encoded data sector 202 is read from storage device 24, and if the read ECC coding flag is cleared, a 512 byte original data sector 200 is read from storage device 24. At 510, host processor 26 receives the data from storage device 24 and storage device 24 signals host processor 26 to indicate that the data has been transferred”; para. [0107], lines 1-2, “the read ECC coding flag is set, a 640 byte ECC encoded data sector 202 is read from storage device 24, and if the read ECC coding flag is cleared, a 512 byte original data sector 200 is read from storage device 24. At 510, host processor 26 receives the data from storage device 24 and storage device 24 signals host processor 26 to indicate that the data has been transferred”; the read ECC coding flag equates to an indication of an error).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Helmick to incorporate the teachings of Hu by including the functionality of transmitting an address error indication to a host device.
The suggestion/motivation for doing so is that it is a predictable design choice to notify a host device of an error during error detection operations in memory.
Claim 25 is a method with limitations similar to the method of claim 21, and is rejected under the same rationale.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Moyer, in view of Pline, further in view of Spencer, further in view of JEDEC.
Regarding claim 18, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 11, but fails to teach further comprising: receiving, as part of an activate command, a row address associated with the data and a bank address associated with the data, wherein receiving the read command is based at least in part on receiving the activate command.
However, JEDEC teaches further comprising: receiving, as part of an activate command, a row address associated with the data and a bank address associated with the data (JEDEC, pg. 7, para. 3, lines 4-6, "Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command"), wherein receiving the read command is based at least in part on receiving the activate command (JEDEC, pg. 19, para. 4, lines 1-3, "The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access").
Moyer, Pline, Spencer and JEDEC are considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices and error correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer in view of Pline, further in view of Spencer to incorporate the teachings of JEDEC by including the functionality of using an activate command to get a row address and bank address.
The suggestion/motivation for doing so would be a predictable design choice necessary for operating industry-standard DRAM devices, allowing a memory system to perform ECC protection along with standard command sequences.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Moyer, in view of Pline, further in view of Spencer, further in view of Helmick et al. (US 10,339,343), hereinafter Helmick.
Regarding claim 19, the combination of Moyer, in view of Pline, further in view of Spencer teaches the method of claim 11, but fails to teach wherein performing the error control operation comprises: determining whether the first codeword matches the third codeword (Helmick, Fig. 8, block 850; the corrected EDC equates to a third codeword).
However, Helmick, in an analogous art, teaches wherein performing the error control operation comprises: determining whether the first codeword matches the third codeword (Helmick, Fig. 8, block 850; the corrected EDC equates to a third codeword).
Moyer, Pline, Spencer, and Helmick are considered to be analogous to the claimed invention because they are in the same field of memory systems that use error-correction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Moyer in view of Pline, further in view of Spencer, to incorporate the teachings of Helmick by including the functionality of determining whether a codeword matches another codeword that was generated from an error correction process.
The suggestion/motivation for doing so would be to determine the effectiveness of the error correction process, and whether the data was corrected.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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