DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Election/Restriction filed on 08/20/2026.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group A, Species I, claims 1-10, in the reply filed on 08/20/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/02/2024, 12/12/2024, 08/20/2025 and 09/04/2025 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 10, the instant claim recites “wherein the second active layer has a second channel length corresponding to a thickness of the second active layer” (claim 10, lines 1-2). Claim 10 depends from claim 6, which introduces only “a second active layer between the drain electrode and the blocking insulating film.” Neither claim 10 nor intervening claims 6, 3 and 1 recite any structure that forms or controls a second channel in the second active layer - i.e., the second source electrode (claim 7) and the second gate electrode (claim 8) that, per the specification (Fig. 12), bound and induce the second channel. Absent those terminals, it is unclear between which electrodes the “second channel length” is measured and what structure establishes that the length “corresponds to” the thickness of the second active layer, so the metes and bounds of the claim cannot be determined. Clarification and/or correction are/is required. For the purpose of examination, claim 10 will be interpreted as if it depended from claim 8, such that the second channel extends through the thickness of the second active layer between the drain electrode and the second source electrode under control of the second gate electrode.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2016/0211281 A1 (Ryu).
Regarding claim 1, Ryu discloses, a thin film transistor (700; thin film transistor substrate; Fig. 20; [0142] - [0146]), comprising:
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a first gate electrode (703; gate electrode; Fig. 20; [0143], [0046]) on a substrate (701; base substrate; Ryu Fig. 20; [0143], [0045]);
a gate insulating film (704; gate insulation layer; Fig. 20; [0143]) on the first gate electrode (703);
a first active layer (705; channel layer; Fig. 20; [0144], [0052]) on the gate insulating film (704);
a drain electrode (707; drain electrode; Fig. 20; [0144] - [0146]) on one side of the first active layer (705);
a sidewall spacer (708; spacer; Fig. 20; [0143], [0146]) on a sidewall of the drain electrode (707);
a first source electrode (706; source electrode; Fig. 20; [0144] - [0145]) provided on another side of the first active layer (705) and a sidewall of the sidewall spacer (708).
Regarding claim 2, Ryu discloses, the thin film transistor of claim 1, wherein the first active layer has a first channel length corresponding to a bottom thickness of the sidewall spacer. Ryu teaches that, because the source and drain electrodes are spaced apart by the spacer, the channel length CL is “defined as a width of an end of the spacer” that contacts the channel layer, i.e., the spacer's bottom thickness, about 0.01 μm to about 1 μm (708; spacer; Fig. 20; [0067] - [0068], [0143]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0211281 A1 (Ryu) and further in view of US 2013/0161732 A1 (Hwang1).
Regarding claim 3, Ryu teaches, the thin film transistor of claim 1 and further teaches that spacer (708) may cover a portion of the upper surface of drain electrode (707), that the spacer may be an insulation material such as silicon oxide or silicon nitride formed in an additional masked process (108; spacer; Fig. 2; [0065], [0100]), and that the spacer may have a multiple-layered structure (108; spacer; Fig. 2; [0066]).
But Ryu fails to teach explicitly, a blocking insulating film on the drain electrode,
However, in analogous art, Hwang1 discloses, a vertical-channel thin film transistor in which an insulating first spacer (130; first spacer; Fig. 1; [0006]-[0007]) is formed on drain electrode (120; drain electrode; Fig. 1; [0006]) and source electrode 140 is formed on the first spacer 130, the source-drain distance being set by the thickness of the first spacer (130). Hwang1 further recognizes that where the source and drain electrodes overlap with only a thin insulator between them, a leakage current or very large parasitic capacitance may be generated ([0022]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ryu and Hwang1 before him/her, to form an insulating film, as taught by Hwang1, on the upper surface of Ryu's drain electrode 707 beneath the portion of source electrode 706 that overlaps the drain electrode, because such a film increases the source-drain separation in the overlap region and thereby suppresses the leakage current and parasitic capacitance that Hwang1 attributes to a thin inter-electrode insulator ([0022]), while the channel length remains set by the bottom width of sidewall spacer 708 (Ryu, [0067]). Absent this important teaching in Ryu, a person with ordinary skill in the art would be motivated to reach out to Hwang1 while forming the thin film transistor of Ryu.
Regarding claim 4, the combination of Ryu and Hwang1 teaches, the thin film transistor of claim 3, wherein the first source electrode is provided on the blocking insulating film (Fig. 20; [0143] - [0145]). Ryu teaches source electrode 706 covering a portion of the upper surface of drain electrode 707 (706; source electrode; Ryu Fig. 20; [0145]); Hwang1 teaches source electrode 140 formed on the insulating first spacer 130 over the drain electrode (120). In the combination, the portion of source electrode 706 over drain electrode 707 lies on the blocking insulating film.
Allowable Subject Matter
Claims 5-10 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the closest prior art, US 2016/0211281 A1 (Ryu), in conjunction with US 2013/0161732 A1 (Hwang1), and in combination with the other claimed features, fails to disclose, “further comprising an upper electrode between the blocking insulating film and the first source electrode”, in combination with the additionally claimed features, as are claimed by the Applicant. Ryu's source electrode 706 lies directly on spacer 708 over the drain electrode, and Hwang1's insulating first spacer 130 carries only the source electrode itself; neither reference provides a separate conductive layer interposed between an insulating film on the drain electrode and a source electrode that also contacts the active layer beyond a sidewall spacer.
Specifically, the aforementioned ‘upper electrode between the blocking insulating film and the first source electrode,’ is material to the inventive concept of the application at hand, which forms a drain electrode / blocking insulating film / upper electrode stack whose sidewall carries a self-aligned sidewall spacer, so that the first source electrode contacts both the upper electrode and the active layer while the channel length is fixed by the spacer bottom thickness.
Regarding claim 6, the closest prior art, US 2016/0211281 A1 (Ryu), in conjunction with US 2013/0161732 A1 (Hwang1), and in combination with the other claimed features, fails to disclose, “the thin film transistor of claim 3, further comprising a second active layer between the drain electrode and the blocking insulating film.
Specifically, the aforementioned ‘second active layer between the drain electrode and the blocking insulating film,’ is material to the inventive concept of the application at hand, which adds a second, vertically oriented channel whose length is set by the second active layer thickness and which is gated through the sidewall spacer, further reducing TFT footprint alongside the spacer-defined first channel.
Claims 7-10 are also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. US 2006/0175609 A1 (Chan) – A vertical this film transistor (TFT) structure is provided that allows for a channel length to be scaled down, below that allowed by lateral TFT structures, to nanoscale (i.e., below 100 nm). However, while reducing the channel length, short-channel effects have been found in previous VTFT structures. Aspects of the new vertical TFT structure allow for the suppression of some of the short-channel effects. Advantageously, the capability of defining nanoscale channel length with short-channel effect suppression allows for p-channel vertical TFTs, where previously these were impractical. Furthermore, in aspects of the vertical TFT structure, the gate electrode is entirely vertical and by eliminating the horizontal overlap of the gate electrode over the drain electrode that present in earlier vertical TFT structures, parasitic gate-to-drain capacitance is eliminated. The vertical TFT structure provides size advantages over lateral TFTs and, furthermore, allows a TFT to be built at the intersection of electrode lines in an active-matrix configuration..
2. US 2022/0199836 A1 (Hwang2) – A vertical channel thin film transistor is disclosed that includes a substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.
3. US 2010/0047984 A1 (Cohen) – A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
AU 2812
09/22/2026
Prosecution Insights