DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/2/2024 and 11/07/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. US 2007/0059502 in view of Sun et al. US 2006/0063375 and Lee et al. US 2004/0224475.
Re claim 1, Wang teaches a method of fabricating a semiconductor device (fig10), comprising:
providing an interlayer dielectric layer (86, fig10, [8]) with a trench (88, fig10, [8]) on a substrate (84, fig10, [8]) in a first substrate processing apparatus (PVD used to deposit 182, fig1, [3, 68]) in a vacuum state (vacuum chamber 12, fig1, [3]);
forming a first metal barrier (182 as TaN with PVD, fig10, [3, 68]) in the trench while the substrate is in the first substrate processing apparatus (PVD, fig1, [3, 68]);
Wang does not explicitly show unloading the substrate from the first substrate processing apparatus and exposing the substrate to a non-vacuum environment; providing the substrate in a second substrate processing apparatus of a vacuum state; forming a second metal barrier in the trench in the second substrate processing apparatus; and forming a metal pattern to fill the trench.
Sun teaches forming a second metal barrier (406 Ru-Ta-N with ALD process, fig5, [46]) in the trench in the second substrate processing apparatus (ALD, [46]); and forming a metal pattern to fill the trench (410 Cu, fig5, [50]).
Lee teaches an apparatus with ALD chamber (fig3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wang, Sun and Lee to form Ru-Ta-N, Ru and Cu in a vacuum chamber with ALD apparatus after forming TaN in the PVD apparatus of Wang. The motivation to do so is to form barrier layer and seed layer with uniform thickness (Lee, [10]) and alleviate stress level between interface region and seed region (Sun, [48]).
Re claim 2,Wang modified above teaches the method of claim 1, further comprising forming a liner layer (Sun, ALD Ru 408, fig5) on the second metal barrier (Sun, ALD Ru-Ta-N 406, fig5) in the second substrate processing apparatus (ALD apparatus as Lee), wherein the liner layer comprises cobalt (Co), ruthenium (Ru) (Sun, ALD Ru 408, fig5), or ruthenium-cobalt alloy (Ru-Co Alloy).
Re claim 3, Wang modified above teaches the method of claim 2, wherein each of the first and second metal barriers comprises one of tantalum nitride (TaN) (Wang, 182 as PVD TaN, fig10), tantalum nitride-tantalum alloy (TaN/Ta), or ruthenium-doped tantalum nitride (Ru-doped TaN) (Sun, ALD Ru-Ta-N formed over TaN, fig5 ).
Embodiment of Wang in Fig10 does not explicitly show further comprising forming a seed layer on the liner layer.
Wang teaches ALD/CVD Cu seed layer also used as a plating electrode ([61]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add in an extra Cu seed layer before the final plating process. The motivation to do so is to improve copper continuity in the plating process (Wang, [10, 60]).
Re claim 4, Wang modified above teaches the method of claim 1, wherein further comprising forming a seed layer (Sun, ALD Ru 408, fig5) on the second metal barrier (Sun, ALD Ru-Ta-N 406, fig5) in the second substrate processing apparatus (ALD apparatus as Lee), wherein the seed layer comprises at least one of copper (Cu), titanium (Ti), ruthenium (Ru) (Sun, ALD Ru 408, fig5), molybdenum (Mo), tungsten (W), or copper alloy (Cu Alloy).
Claim(s) 1, 5, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2023/0260770 in view of Wei et al. US 2020/0101580 and Wu et al. US 2016/0040288.
Re claim 1, Tsai teaches a method of fabricating a semiconductor device (600, fig6A-6E, [69]), comprising:
providing an interlayer dielectric layer (606-612, fig6A, [70]) with a trench (616, fig6A, [71]) on a substrate (604, fig6A, [70]) in a first substrate processing apparatus in a vacuum state (ALD chamber 107a/b or PVD chamber 111a used to form 618, fig1 and 6B, [16, 21, 23, 72]);
forming a first metal barrier (618, fig6B, [72]) in the trench while the substrate is in the first substrate processing apparatus (ALD chamber 107a/b or PVD chamber 111a, fig1, [21, 23]);
unloading the substrate from the first substrate processing apparatus (ALD chamber 107a/b or PVD chamber 111a, fig1, [21, 23]) and exposing the substrate to a non-vacuum environment (CMP process in chamber 109, fig1, [22, 72]);
providing the substrate in a second substrate processing apparatus of a vacuum state (PVD chamber 111a or CVD chamber 107a/b used to form 620, fig1 and 6C, [21, 23, 73]);
forming a second metal barrier (620, fig6C, [73]) in the trench in the second substrate processing apparatus; and
forming a metal pattern to fill the trench (622, fig6D, [74]).
Tsai does not explicitly show the environment of the CMP process chamber, ALD chamber and PVD chamber.
Wei teaches CMP process in a non-vacuum environment with momentum vacuum assembly (180, fig2, [43]).
Wu teaches ALD and PVD chamber operate under vacuum state ([38]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai, Wei and Wu to use a CMP chamber as Wei and perform ALD and PVD deposition process under vacuum state. The motivation to do so is to minimize contamination to the ALD and PVD chamber and film deposited (Wu, [52, 98]) and perform CMP process with reduced defects (Wei, [16]).
Re claim 5, Tsai modified above teaches the method of claim 1, wherein further comprising: providing the substrate with the first metal barrier (Tsai, 618, fig6C) in a third substrate processing apparatus in a vacuum state (Tsai, extra etching chamber 109 to perform etching of blocking material before forming liner, fig1 and 6C, [22, 73]; Wu, RF plasma etch with low pressure ion [78]); performing a pre-cleaning process on the substrate in the third substrate processing apparatus (Tsai, extra etching chamber 109 used to remove blocking material, fig1 and 6C, [22, 73]); and unloading the substrate from the third substrate processing apparatus and exposing the substrate to a non-vacuum environment (Tsai, perform CMP in 109, fig1 and 6E, [75]).
Re claim 13, Tsai Wang teaches a method of fabricating a semiconductor device (600, fig6A-6E, [69]), comprising:
providing an interlayer dielectric layer (606-612, fig6A, [70]) with a trench (616, fig6A, [71]) on a substrate (604, fig6A, [70]) in a first substrate processing apparatus in a vacuum state (ALD chamber 107a/b or PVD chamber 111a/b used to form 618, fig1 and 6B, [16, 21, 23, 72]);
forming a deposition suppressing layer (618, fig6B, [72]) in the trench while the substrate is in the first substrate processing apparatus (ALD chamber 107a/b or PVD chamber 111a/b, fig1, [21, 23]);
unloading the substrate from the first substrate processing apparatus (ALD chamber 107a/b or PVD chamber 111a/b, fig1, [21, 23]) to expose the substrate to a non-vacuum state (CMP chamber 109, fig1, [22, 72]);
providing the substrate in a second substrate processing apparatus of a vacuum state (PVD chamber 111a/b or CVD chamber 107a/b used to form 620, fig1 and 6C, [21, 23, 73]);
forming a first metal barrier in the trench (620, fig6C, [73]), in the second substrate processing apparatus (PVD chamber 111a/b or CVD chamber 107a/b used to form 620, fig1 and 6C, [21, 23, 73]); and
forming a metal pattern (622, fig6D, [74]) to fill the trench.
Tsai does not explicitly show the environment of the CMP process chamber, ALD chamber and PVD chamber.
Wei teaches CMP process in a non-vacuum environment with momentum vacuum assembly (180, fig2, [43]).
Wu teaches ALD and PVD chamber operate under vacuum state ([38]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai, Wei and Wu to use a CMP chamber as Wei and perform ALD and PVD deposition process under vacuum state. The motivation to do so is to minimize contamination to the ALD and PVD chamber and film deposited (Wu, [52, 98]) and able to perform CMP process with reduced defects (Wei, [16]).
Re claim 18, Tsai modified above teaches the method of claim 13, further comprising: moving the substrate from the second substrate processing apparatus to a third substrate processing apparatus of a vacuum state (Tsai, extra etching chamber 109 to perform etching of blocking material before forming liner, fig1 and 6C, [22, 73]; Wu, RF plasma etch with low pressure ion [78]); and performing a post-treatment process in the third substrate processing apparatus (Tsai, extra etching chamber 109 used to remove blocking material, fig1 and 6C, [22, 73]).
Claim(s) 2, 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2023/0260770 in view of Wei et al. US 2020/0101580, Wu et al. US 2016/0040288 and Sun et al. US 2006/0063375.
Re claim 2, Tsai does not explicitly show the method of claim 1, further comprising forming a liner layer on the second metal barrier in the second substrate processing apparatus, wherein the liner layer comprises cobalt (Co), ruthenium (Ru), or ruthenium-cobalt alloy (Ru-Co Alloy).
Sun teaches forming TaN with a PVD process ([43]) and forming a second metal barrier (406 Ru-Ta-N with ALD process, fig5, [46]) in the trench in the second substrate processing apparatus (ALD, [46]); forming a metal pattern to fill the trench (410 Cu, fig5, [50]), forming a liner layer (ALD Ru 408, fig5) on the second metal barrier (ALD Ru-Ta-N 406, fig5) in the second substrate processing apparatus (ALD/CVD apparatus as Lee), wherein the liner layer comprises cobalt (Co), ruthenium (Ru) (ALD Ru 408, fig5), or ruthenium-cobalt alloy (Ru-Co Alloy).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai modified above and Sun to form Ru-Ta-N, Ru and Cu in a vacuum chamber with ALD apparatus after forming TaN in the PVD apparatus. The motivation to do so is to form uniform metal (Sun, [33]) and alleviate stress level between interface region and seed region (Sun, [48]).
Re claim 4, Tsai does not explicitly show the method of claim 1, wherein further comprising forming a seed layer on the second metal barrier in the second substrate processing apparatus, wherein the seed layer comprises at least one of copper (Cu), titanium (Ti), ruthenium (Ru), molybdenum (Mo), tungsten (W), or copper alloy (Cu Alloy).
Sun teaches wherein further comprising forming a seed layer (Sun, ALD Ru 408, fig5) on the second metal barrier (Sun, ALD Ru-Ta-N 406, fig5) in the second substrate processing apparatus (ALD/CVD apparatus as Tsai), wherein the seed layer comprises at least one of copper (Cu), titanium (Ti), ruthenium (Ru) (Sun, ALD Ru 408, fig5), molybdenum (Mo), tungsten (W), or copper alloy (Cu Alloy).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai modified above and Sun to form Ru-Ta-N, Ru and Cu in a vacuum chamber with ALD apparatus after forming TaN in the PVD apparatus. The motivation to do so is to form uniform metal (Sun, [33]) and alleviate stress level between interface region and seed region (Sun, [48]).
Re claim 6, Tsai does not explicitly show the method of claim 5, further comprising forming a seed layer on the second metal barrier, after forming the second metal barrier on the substrate.
Sun teaches wherein further comprising forming a seed layer (Sun, ALD Ru 408, fig5) on the second metal barrier (Sun, ALD Ru-Ta-N 406, fig5) in the second substrate processing apparatus (ALD/CVD apparatus as Tsai), wherein the seed layer comprises at least one of copper (Cu), titanium (Ti), ruthenium (Ru) (Sun, ALD Ru 408, fig5), molybdenum (Mo), tungsten (W), or copper alloy (Cu Alloy).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai modified above and Sun to form Ru-Ta-N, Ru and Cu in a vacuum chamber with ALD apparatus after forming TaN in the PVD apparatus. The motivation to do so is to form uniform metal (Sun, [33]) and alleviate stress level between interface region and seed region (Sun, [48]).
Re claim 7, Tsai modified above teaches the method of claim 6, further comprising forming a liner layer on the substrate (Sun, TaRu formed with nitrogen turned off first or RuN formed with Tantalum turned off first, [49]), before forming the seed layer (Sun, 408 Ru, fig5, [48]) on the substrate in the second substrate processing apparatus (ALD chamber as in Tsai).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2023/0260770 in view of Wei et al. US 2020/0101580, Wu et al. US 2016/0040288, Sun et al. US 2006/0063375 and Wang et al. US 2007/0059502
Re claim 3, Tsai does not explicitly show the method of claim 2, further comprising forming a seed layer on the liner layer, wherein each of the first and second metal barriers comprises one of tantalum nitride (TaN), tantalum nitride-tantalum alloy (TaN/Ta), or ruthenium-doped tantalum nitride (Ru-doped TaN).
Sun teaches second metal barrier comprises ruthenium-doped tantalum nitride (Ru-doped TaN) (Sun, ALD Ru-Ta-N formed over TaN, fig5 ).
Wang teaches wherein each of the first metal barrier comprises one of tantalum nitride (TaN) (Wang, 182 as PVD TaN, fig10) and ALD/CVD Cu seed layer also used as a plating electrode ([61]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai modified above and Wang to add in an extra Cu seed layer before the final plating process. The motivation to do so is to improve copper continuity in the plating process (Wang, [10, 60]).
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2023/0260770 in view of Wei et al. US 2020/0101580, Wu et al. US 2016/0040288, Wang et al. US 2007/0059502 and Chung et al. US 2005/0106865.
Re claim 8, Tsai does not explicitly show teaches the method of claim 1, further comprising performing a pre-cleaning process on the substrate in the second substrate processing apparatus, before forming the second metal barrier on the substrate.
Wang teaches performing a punch through step in PVD chamber ([58]).
Chung teaches forming a first metal barrier (ALD TaN 912, fig9B, [47]), performing a pre-cleaning process (punch through step, fig9D, [69]), before forming the second metal barrier (PVD Ta flash, fig9E, [73]) on the substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai modified above with Wang and Chung to add in a punch through step in the PVD chamber after the ALD TaN step and before PVD Ta step. The motivation to do so is to reduce the contact resistance (Chung, [8]), simplify process and improved performance (Wang, [88]).
Re claim 9, Tsai modified above teaches the method of claim 8, further comprising forming a seed layer (Chung, PVD 1004 Cu seed over ALD TaN 1001, fig2 and 10, [78, 81]; or Wang, 114 PVD Cu seed layer over 182 ALD TaN, fig10, [60, 68]) on the second metal barrier (Chung, PVD Ta 1005 at step 206, fig1 and 10, [64, 80]; or Wang, PVD 184, fig10, [44, 68]) in the second substrate processing apparatus (PVD chamber as in Tsai).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2023/0260770 in view of Wei et al. US 2020/0101580, Wu et al. US 2016/0040288, and Wang et al. US 2007/0059502.
Re claim 16, Tsai modified above teaches the method of claim 13, further comprising: unloading the substrate from the second substrate processing apparatus and exposing the substrate to a non-vacuum environment (Tsai, place substrate in CMP chamber for planarization of 620, fig6C, [73]);
Tsai does not explicitly show providing the substrate in a third substrate processing apparatus of a vacuum state; and forming a seed layer on the substrate.
Wang teaches forming tantalum nitride layer (TaN) (182 as ALD TaN, fig10, [68]), first metal barrier as RuTa (PVD RuTa 184, fig10, [44, 68]) and CVD Cu seed layer also used as a plating electrode ([61]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai modified above and Wang to add in an extra Cu seed layer formed in a CVD vacuum chamber before the final plating process. The motivation to do so is to improve copper continuity in the plating process (Wang, [10, 60]).
Allowable Subject Matter
Claim 10-12, 14-15, 17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to form a laminated barrier structure with low resistance and prevent diffusion to the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOMING LIU/Examiner, Art Unit 2812
