Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/2/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims: 1-2; and 14-15 of U.S. Patent No. 12,087,682 (Elsherbini). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 is not patentably distinct from Elsherbini.
Instant Application 18/762,484
U.S. Patent No. 12, 087,682
(Claim 1) An integrated circuit assembly, comprising:
(Claim 1) An integrated circuit assembly, comprising:
(Claim 1) an electronic substrate having a first surface;
(Claim 1) an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface,
(Claim 1) an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface,
(Claim 1) wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate;
(Claim 1) wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate;
(Claim 1) a plurality of first and second through-substrate vias extending into the IC device from the second surface thereof;
(Claim 2, inserted) The integrated circuit assembly of claim 1, wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.
(Claim 1) a power route electrically attached to the first through-substrate vias at the second surface of the IC device; and a ground route electrically attached to the second through-substrate vias at the second surface of the IC device,
(Claim 2, inserted, duplicated from above for clarity) The integrated circuit assembly of claim 1, wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.in combination with (Claim 1) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate, and wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.
(Claim 1, duplicated from above for clarity) a power route electrically attached to the first through-substrate vias at the second surface of the IC device; and a ground route electrically attached to the second through-substrate vias at the second surface of the IC device,
(Claim 1, duplicated from above for clarity) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate,
(Claim 1) wherein the power route and the ground route are conformal to the side of the IC device and conformal to the first surface of the electronic substrate.
(Claim 1, duplicated from above for clarity) wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate,
Instant Application 18/762,484
U.S. Patent No. 12, 087,682
(Claim 1) An integrated circuit assembly, comprising:
(Claim 14) An integrated circuit assembly, comprising:
(Claim 1) an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface,
(Claim 14) an electronic substrate having a first surface; an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface,
(Claim 1) wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate;
(Claim 14) an electronic substrate having a first surface; [...] wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate;
(Claim 1) a plurality of first and second through-substrate vias extending into the IC device from the second surface thereof; a power route electrically attached to the first through-substrate vias at the second surface of the IC device; and a ground route electrically attached to the second through-substrate vias at the second surface of the IC device,
(Claim 15, inserted) The integrated circuit assembly of claim 14, wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.
(Claim 1, duplicated from above for clarity) a plurality of first and second through-substrate vias extending into the IC device from the second surface thereof; a power route electrically attached to the first through-substrate vias at the second surface of the IC device; and a ground route electrically attached to the second through-substrate vias at the second surface of the IC device,
(Claim 14) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate,
(Claim 1) wherein the power route and the ground route are conformal to the side of the IC device and conformal to the first surface of the electronic substrate.
(Claim 14) wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate, and wherein the at least one power delivery route is non-linear on the second surface of the integrated circuit device.
Claims 11 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims: 1, 6-7, 12, 14, and 20 of U.S. Patent No. 12,087,682 (Elsherbini). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 is not patentably distinct from Elsherbini.
Instant Application 18/762,484
U.S. Patent No. 12, 087,682
(Claim 11) An integrated circuit assembly, comprising:
(Claim 1) An integrated circuit assembly, comprising:
an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface, wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate;
(Claim 1) an electronic substrate having a first surface;
(Claim 11) an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface,
(Claim 1) an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface,
(Claim 11) wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate; a plurality of first and second connections at the second surface of the IC device;
(Claim 1) wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate;
(Claim 11) a power route electrically attached to the first connections at the second surface of the IC device; and a ground route electrically attached to the second connections at the second surface of the IC device,
(Claim 1) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate, and wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.
(Claim 11) wherein the power route and the ground route are conformal to the side of the IC device and conformal to the first surface of the electronic substrate.
(Claim 1, duplicated from above for clarity) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate, and wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.
(Claim 14) The integrated circuit assembly of claim 11, further comprising a stacked power route and a stacked ground route over the power route and the ground route.
(Claim 6) The integrated circuit assembly of claim 1, further comprising at least one stacked power delivery route in a stacked configuration with and electrically attached to the at least one power delivery route on the second surface of the integrated circuit device.
Instant Application 18/762,484
U.S. Patent No. 12, 087,682
(Claim 11) An integrated circuit assembly, comprising:
(Claim 7) An electronic system, comprising: an electronic board having a first surface; an integrated circuit assembly comprising:
(Claim 11) an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface, wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate;
(Claim 7) an electronic substrate having a first surface and an opposing second surface and at least one side extending between the first surface and the second surface of the electronic substrate; and an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface; wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate, wherein the second surface of the electronic substrate of the integrated circuit assembly is electrically attached to the first surface of the electronic board,
(Claim 11) a plurality of first and second connections at the second surface of the IC device; a power route electrically attached to the first connections at the second surface of the IC device; and a ground route electrically attached to the second connections at the second surface of the IC device,
(Claim 12, inserted) The electronic system of claim 7, wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.
(Claim 7) and wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof;
(Claim 11, duplicated from above for clarity) a plurality of first and second connections at the second surface of the IC device; a power route electrically attached to the first connections at the second surface of the IC device; and a ground route electrically attached to the second connections at the second surface of the IC device,
(Claim 7) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and electrically attached to the first surface of the electronic board,
(Claim 11) wherein the power route and the ground route are conformal to the side of the IC device and conformal to the first surface of the electronic substrate.
(Claim 7) wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device, at least a portion of the first surface of the electronic substrate, at least a portion of the at least one side of the electronic substrate, and at least a portion of the first surface of the electronic board, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.
Instant Application 18/762,484
U.S. Patent No. 12, 087,682
(Claim 11) An integrated circuit assembly, comprising:
(Claim 14) An integrated circuit assembly, comprising:
(Claim 11) an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface, wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate;
(Claim 14) an electronic substrate having a first surface;
(Claim 11, duplicated rom above for clarity) an integrated circuit (IC) device having a first surface, an opposing second surface, and a side extending between the first surface and the second surface,
(Claim 14) an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface,
(Claim 11) wherein the first surface of the IC device is electrically attached to a first surface of an electronic substrate;
(Claim 14) wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate;
(Claim 11) a plurality of first and second connections at the second surface of the IC device; a power route electrically attached to the first connections at the second surface of the IC device; and a ground route electrically attached to the second connections at the second surface of the IC device,
(Claim 14) and at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate,
(Claim 11) wherein the power route and the ground route are conformal to the side of the IC device and conformal to the first surface of the electronic substrate.
(Claim 14) wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate,
(Claim 14) and wherein the at least one power delivery route is non-linear on the second surface of the integrated circuit device.
(Claim 14) The integrated circuit assembly of claim 11, further comprising a stacked power route and a stacked ground route over the power route and the ground route.
(Claim 20) The integrated circuit assembly of claim 14, further comprising at least one stacked power delivery route in a stacked configuration with and electrically attached to the at least one power delivery route on the second surface of the integrated circuit device.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-7, 9, 11-12, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 20120086109 A1, from IDS).
Regarding claim 1, Kim discloses an integrated circuit assembly (Fig. 1a), comprising:
an integrated circuit (IC) device (110) having a first surface (See annotated figure), an opposing second surface (See annotated figure), and a side (See annotated figure) extending between the first surface and the second surface, wherein the first surface of the IC device is electrically attached (“attached” by 144) to a first surface of an electronic substrate (160);
a plurality of first and second through-substrate vias (120a, 120b) extending into the IC device from the second surface thereof;
a power route (150a; [0041]: “first ground voltage”) electrically attached ([0041]: “may be connected”) to the first through-substrate vias at the second surface of the IC device; and
a ground route (150b; [0041]: “second ground voltage”) electrically attached ([0041]: “may be connected”) to the second through-substrate vias at the second surface of the IC device, wherein the power route and the ground route are conformal (at least partially “conformal”) to the side of the IC device and conformal (at least partially “conformal”) to the first surface of the electronic substrate.
Illustrated below is a marked and annotated figure of Fig. 1a of Kim.
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Regarding claim 2, Kim discloses the integrated circuit assembly of claim 1 (Fig. 1a), wherein the first through-substrate vias are in a first row (into the page, at least some number of vias) across at least a portion of the second surface of the IC device, the second through- substrate vias are in a second row (into the page, at least some number of vias) across the portion of the second surface of the IC device adjacent to the first row.
Regarding claim 9, Kim discloses the integrated circuit assembly of claim 1 (Fig. 12a), further comprising an electronic board (1010) having a first surface electrically attached (“attached” by Fig. 1a: 168) to the electronic substrate.
Illustrated below is Fig. 12a of Kim.
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Regarding claim 6, Kim discloses the integrated circuit assembly of claim 1 (Fig. 12a), further comprising: a power delivery device (1040) attached (indirectly “attached” through intervening 1010) to the first surface of the electronic substrate and electrically coupled (“coupled” through 1012) to the power route.
Regarding claim 7, Kim discloses the integrated circuit assembly of claim 6 (Fig. 12a), wherein the power delivery device comprises one of a voltage regulator, an inductor, or a capacitor ([0113]: “decoupling capacitor”).
Regarding independent claim 11, Kim discloses an integrated circuit assembly (Fig. 1a), comprising:
an integrated circuit (IC) device (110) having a first surface (See annotated figure), an opposing second surface (See annotated figure), and a side (See annotated figure) extending between the first surface and the second surface, wherein the first surface of the IC device is electrically attached (“attached” by 144) to a first surface of an electronic substrate (160);
a plurality of first and second connections (See annotated figure) at the second surface of the IC device;
a power route (150a; [0041]: “first ground voltage”) electrically attached ([0041]: “may be connected”) to the first connections at the second surface of the IC device; and
a ground route (150b; [0041]: “second ground voltage”) electrically attached ([0041]: “may be connected”) to the second connections at the second surface of the IC device, wherein the power route and the ground route are conformal (at least partially “conformal”) to the side of the IC device and conformal (at least partially “conformal”) to the first surface of the electronic substrate.
Regarding claim 12, Kim discloses the integrated circuit assembly of claim 11 (Fig. 1a), wherein the first connections are in a first row (into the page, at least some number of vias) across at least a portion of the second surface of the IC device, the second connections are in a second row (into the page, at least some number of vias) across the portion of the second surface of the IC device adjacent to the first row.
Regarding claim 19, Kim discloses the integrated circuit assembly of claim 11 (Fig. 12a), further comprising an electronic board (1010) having a first surface electrically attached (“attached” by Fig. 1a: 168) to the electronic substrate.
Regarding claim 16, Kim discloses the integrated circuit assembly of claim 11 (Fig. 12a), further comprising: a power delivery device (1040) attached (indirectly “attached” through intervening 1010) to the first surface of the electronic substrate and electrically coupled (“coupled” through 1012) to the power route.
Regarding claim 17, Kim discloses the integrated circuit assembly of claim 16 (Fig. 12a), wherein the power delivery device comprises one of a voltage regulator, an inductor, or a capacitor ([0113]: “decoupling capacitor”).
Allowable Subject Matter
Claims 3-5, 8, 10, 13, 15, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 3 is the inclusion of the limitation “wherein the power route is one of a plurality of power routes each coupled to a plurality of power through-substrate vias, the ground route is one of a plurality of ground routes each coupled to a plurality of ground through-substrate vias, and the power routes and the ground routes alternate across the second surface of the IC device” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “coupled to a plurality of power through-substrate vias”, “coupled to a plurality of ground through-substrate vias”, and “alternate” in combination with all other limitations in claims 3 and 1. The claimed shape and arrangement and electrical configuration of routes were determined to be enabled by the collective teachings found elsewhere in the prior art; however, the particularly claimed combination of limitations was not explicitly found, suggested, or reasonably rendered obvious by the prior art. MPEP 2144.04 (IV)(B); MPEP 2144.04 (VI)(C).
The primary reason for the allowable subject matter of claims 4-5 is the inclusion of the limitation “further comprising a stacked power route and a stacked ground route over the power route and the ground route” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “stacked power route” and “stacked ground route” in combination with all other limitations in claims 4 and 1. The claimed arrangement and electrical configuration of routes were determined to be enabled by the collective teachings found elsewhere in the prior art; however, the particularly claimed combination of limitations was not explicitly found, suggested, or reasonably rendered obvious by the prior art. MPEP 2144.04 (VI)(C); MPEP 2114 (III).
The primary reason for the allowable subject matter of claim 8 is the inclusion of the limitation “wherein the power route is conformal to a top surface of the power delivery device” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “power route” and “conformal to a top surface of the power delivery device” in combination with all other limitations in claims 8, 6, and 1. The prior art discloses electrical connections with power delivery devices; however, the electrical connection formed by the claimed “conformal” shape requires a configuration of one of the routes that was not disclosed in the prior art when this configuration was considered in combination with all other limitations required by the claim. MPEP 2144.04 (IV)(B).
The primary reason for the allowable subject matter of claim 10 is the inclusion of the limitation “wherein one of the power route and the ground route are conformal to the first surface of the electronic board” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “one of the power route and the ground route” and “conformal to the first surface of the electronic board” in combination with all other limitations in claims 10, 9, and 1. The prior art discloses electrical connections with electronic boards; however, the electrical connection formed by the claimed “conformal” shape requires a configuration of one of the routes that was not disclosed in the prior art when this configuration was considered in combination with all other limitations required by the claim. MPEP 2144.04 (IV)(B).
The primary reason for the allowable subject matter of claim 13 is the inclusion of the limitation “wherein the power route is one of a plurality of power routes each coupled to a plurality of power connections, the ground route is one of a plurality of ground routes each coupled to a plurality of ground connections, and the power routes and the ground routes alternate across the second surface of the IC device” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “coupled to a plurality of power connections”, “coupled to a plurality of ground connections”, and “alternate” in combination with all other limitations in claims 13 and 11. The claimed shape and arrangement and electrical configuration of routes were determined to be enabled by the collective teachings found elsewhere in the prior art; however, the particularly claimed combination of limitations was not explicitly found, suggested, or reasonably rendered obvious by the prior art. MPEP 2144.04 (IV)(B); MPEP 2144.04 (VI)(C).
The primary reason for the allowable subject matter of claim 15 is the inclusion of the limitation “wherein the power route and the ground route extend across the second surface of the IC device in a first direction, and the stacked power route and the stacked ground route extend across the second surface of the IC device in a second direction orthogonal to the first direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “stacked power route” and “stacked ground route” in combination with all other limitations in claims 15, 14, and 11. The claimed arrangement and electrical configuration of routes were determined to be enabled by the collective teachings found elsewhere in the prior art; however, the particularly claimed combination of limitations was not explicitly found, suggested, or reasonably rendered obvious by the prior art. MPEP 2144.04 (VI)(C); MPEP 2114 (III).
The primary reason for the allowable subject matter of claim 18 is the inclusion of the limitation “wherein the power route is conformal to a top surface of the power delivery device” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “power route” and “conformal to a top surface of the power delivery device” in combination with all other limitations in claims 18, 16, and 11. The prior art discloses electrical connections with power delivery devices; however, the electrical connection formed by the claimed “conformal” shape requires a configuration of one of the routes that was not disclosed in the prior art when this configuration was considered in combination with all other limitations required by the claim. MPEP 2144.04 (IV)(B).
The primary reason for the allowable subject matter of claim 20 is the inclusion of the limitation “wherein one of the power route and the ground route are conformal to the first surface of the electronic board” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “one of the power route and the ground route” and “conformal to the first surface of the electronic board” in combination with all other limitations in claims 20, 19, and 11. The prior art discloses electrical connections with electronic boards; however, the electrical connection formed by the claimed “conformal” shape requires a configuration of one of the routes that was not disclosed in the prior art when this configuration was considered in combination with all other limitations required by the claim. MPEP 2144.04 (IV)(B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Primary Examiner, Art Unit 2817
