Prosecution Insights
Last updated: October 02, 2026
Application No. 18/762,685

PACKAGE HAVING REDISTRIBUTION LAYER STRUCTURE WITH PROTECTIVE LAYER AND METHOD OF FABRICATING THE SAME

Final Rejection §102§112
Filed
Jul 03, 2024
Priority
Aug 28, 2018 — continuation of 11/031,344 +2 more
Examiner
CROSS, XIA L
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
389 granted / 471 resolved
+14.6% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
14 currently pending
Career history
481
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 471 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 Examiner acknowledges the amendment to claim 15 filed on June 19, 2026. The 35 U.S.C. § 112 rejections in the previous Office Action filed on February 19, 2026 are hereby withdrawn. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 15, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hou et al. (US PG-Pub No.: 2014/0252572 A1, hereinafter, “Hou”). Regarding claim 15, Hou discloses a package (see Hou, FIG, 2e), comprising: a circuit substrate (30, FIG. 2e) comprising a first substrate side (bottom of 30), a second substrate side (top of 30) opposite the first substrate side (bottom of 30), and a first lateral substrate side (left of 30) that extends between the first substrate side (bottom of 30) and the second substrate side (top of 30); an electronic device (120, FIG. 2e) comprising a first device side (bottom of 120) facing toward the second substrate side (top of 30), a second device side (top of 120) opposite the first device side (bottom of 120), and a first lateral device side (left of 130) that extends between the first device side (bottom of 120) and the second device side (top of 120); wherein the electronic device (120) comprises: a first conductive pattern (left 60, FIG. 2e and labelled in FIG. 2d) comprising a first conductive pattern side (bottom of left 60) facing toward the circuit substrate (30), a second conductive pattern side (top of left 60) opposite the first conductive pattern side (bottom of left 60), and a first lateral conductive pattern side (left of left 60) that extends between the first conductive pattern side (bottom of left 60) and the second conductive pattern side (top of left 60); a first barrier structure (left 80, FIG. 2e and labelled in FIG. 2d) overlying the first lateral conductive pattern side (left of left 60) and the second conductive pattern side (top of left 60, FIG. 2e); a second conductive pattern (right 60, FIG. 2e) aside the first conductive pattern (left 60) and comprising a third conductive pattern side (bottom of right 60) facing toward the circuit substrate (30), a fourth conductive pattern side (top of right 60) opposite the third conductive pattern side (bottom of right 60), and a second lateral conductive pattern side (left of right 60) that extends between the third conductive pattern side (bottom of right 60) and the fourth conductive pattern side (top of right 60, FIG. 2e); and a second barrier structure (right 80, FIG, 2e) overlying the second lateral conductive pattern side (left of right 60); and an underfill (70, FIG. 2e) disposed between the electronic device (120) and the circuit substrate (30) to laterally encapsulate a plurality of conductive connectors (60+80), wherein the underfill (70) has an inclined sidewall extending outward away from the first lateral device side (bottom of 120) to the second substrate side (top of 30, FIG. 2e). Regarding claim 17, Hou discloses the package of claim 15, wherein the first conductive pattern side (bottom of left 60) is free of the first barrier structure (in order to meet the limitation, the first barrier structure is 94). Regarding claim 20, Hou discloses the package of claim 15, further comprising: one or more dies (120 has multiple layers, ¶ [0014]) over the second conductive pattern side of the first conductive pattern (top of left 60) and the fourth conductive pattern side of the second conductive pattern (top of right 60); and an encapsulant (94) encapsulating the one or more dies (120, FIG. 2e). Allowable Subject Matter Claims 1-14 are allowed. Claims 16 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 1, in particular, after the forming the plurality of first traces, forming a protective layer on the plurality of first traces, wherein the protective layer covers top surfaces of the plurality of first traces and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to remove a portion of the second dielectric material and a portion of the protective layer until the plurality of first traces are exposed. Therefore, claim 1 is allowable. Accordingly, claims 2-8 are allowable as they depend upon claim 1. The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 9, in particular, a first pillar structure embedded in the second dielectric material and extending on a top surface of the first dielectric material without penetrating through the top surface of the first dielectric material; a second pillar structure aside the first pillar structure, wherein the second pillar structure penetrates through the first dielectric material and the second dielectric material to be in contact with the conductive pad of the die at the topmost surface; and a protective layer extending between a side surface of the first pillar structure and a side surface of an upper portion of the second pillar structure. Therefore, claim 9 is allowable. Accordingly, claims 10-14 are allowable as they depend upon claim 9. The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 16, in particular, the first barrier structure comprises: a first seed metal contacting the first lateral conductive pattern side and the second conductive pattern side; and a first protective layer overlying an outer surface of the first seed metal, so that the first protective layer completely covers the first lateral conductive pattern side and the second conductive pattern side without covering the first conductive pattern side. Therefore, claim 16 is allowable. Accordingly, claims 18-19 are allowable as they depend upon claim 16. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIA L CROSS/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jul 03, 2024
Application Filed
Jan 08, 2026
Non-Final Rejection (signed) — §102, §112
Feb 19, 2026
Non-Final Rejection mailed — §102, §112
Jun 19, 2026
Response Filed
Sep 10, 2026
Final Rejection mailed — §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
91%
With Interview (+8.7%)
2y 4m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 471 resolved cases by this examiner. Grant probability derived from career allowance rate.

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