DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 7/03/24. Claims 1-20 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 8/08/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 9-16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tokuhira et al. (US PGPub 2020/0185395, hereinafter referred to as “Tokuhira”).
Tokuhira discloses the semiconductor device as claimed. See figures 1A-11D and corresponding text, where Tokuhira teaches, in claim 1, a semiconductor memory device comprising:
a semiconductor layer (51);
a gate electrode facing the semiconductor layer (51);
a first insulating film (42) provided between the semiconductor layer (51) and the gate electrode, and including at least one of oxygen (O), hafnium (Hf), or a first additive element, the first insulating film (42) formed with an orthorhombic crystal structure (figures 1A and 1B; [0025]); and
a second insulating film (61) provided between the first insulating film (42) and the gate electrode, wherein the first insulating film (42) includes a first additive region, a second additive region provided between the first additive region and the gate electrode, and a memory region (40) provided between the first additive region and the second additive region, the first additive region includes a second additive element selected from a group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), platinum (Pt), and combinations thereof, the second additive region includes a third additive element selected from a group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), platinum (Pt), and combinations thereof, the memory region (40) does not include the second additive element, or a concentration of the second additive element in the memory region is lower than a concentration of the second additive element in the first additive region, and the memory region does not include the third additive element, or a concentration of the third additive element in the memory region is lower than a concentration of the third additive element in the second additive region (figures 1A and 1B; [0011] [0025-0026]).
Tokuhira teaches, in claim 2, wherein the first insulating film (42) includes the first additive element selected from a group consisting of silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), barium (Ba), and combinations thereof (figures 1A and 1B; [0011] [0025-0026]).
Tokuhira teaches, in claim 3, wherein the first additive region includes a surface of the first insulating film (42) on a side of the semiconductor layer (51), and the second additive region includes a surface of the first insulating film (42) on a side of the gate electrode (figures 1A and 1B; [0011] [0025-0026]).
Tokuhira teaches, in claim 4, wherein the first insulating film (42) includes a region provided between the second additive region and the gate electrode, the first additive region includes a surface of the first insulating film (42) on a side of the semiconductor layer (51), and the region includes a surface of the first insulating film (42) on a side of the gate electrode.
Tokuhira teaches, in claim 7, a semiconductor memory device comprising:
a plurality of conductive layers (11) and a plurality of insulating layers (12) alternately stacked in a stacking direction (figures 1A and 1B; [0011], [0031-0032]);
a semiconductor layer (51) extending in the stacking direction and facing the plurality of conductive layers (11) (figures 1A and 1B; [0034-0035]);
an insulating film (42) provided between the plurality of conductive layers and the semiconductor layer (51), extending in the stacking direction, and including at least one of oxygen (O) or hafnium (Hf), the insulating film formed with an orthorhombic crystal structure; and
a boundary layer provided between the insulating film and the semiconductor layer and extending in the stacking direction, wherein the boundary layer includes a plurality of first portions provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction, respectively, and a plurality of second portions provided at a plurality of positions corresponding to the plurality of insulating layers in the stacking direction, respectively, and a distance from the plurality of second portions to the semiconductor layer is greater than a distance from the plurality of first portions to the semiconductor layer (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 9, wherein the insulating film includes a plurality of third portions provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction, respectively, and a plurality of fourth portions provided at a plurality of positions corresponding to the plurality of insulating layers in the stacking direction, respectively, and a distance from the plurality of fourth portions to the semiconductor layer is greater than a distance from the plurality of third portions to the semiconductor layer (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 10, further comprising:
a plurality of insulating members arranged along a surface of the semiconductor layer on a side of the plurality of conductive layers and in the stacking direction corresponding to the plurality of insulating layers, respectively, wherein the boundary layer extends in the stacking direction along surfaces of the semiconductor layer and the plurality of insulating members on the side of the plurality of conductive layers, and the insulating film extends in the stacking direction along a surface of the boundary layer on the side of the plurality of conductive layers (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 11, wherein the insulating film includes an additive region, and the additive region includes an additive element selected from a group consisting of ruthenium (Ru), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), platinum (Pt), and combinations thereof (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 12, wherein the additive region extends in the stacking direction over a range in the stacking direction corresponding to the plurality of conductive layers (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 13, further comprising: a plurality of the additive regions provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction, respectively (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 14, wherein the insulating film includes a plurality of portions provided at a plurality of positions corresponding to the plurality of conductive layers in the stacking direction, respectively, and including a structure that are orthorhombic as a crystal structure, and a plurality of other portions provided at a plurality of positions corresponding to the plurality of insulating layers in the stacking direction, respectively, and including a structure that are not orthorhombic as a crystal structure (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 15, a semiconductor memory device comprising:
a plurality of conductive layers (11) and a plurality of insulating layers (12) alternately stacked in a stacking direction;
a semiconductor layer (51) extending in the stacking direction and facing the plurality of conductive layers (11); and
an insulating film (42) provided between the plurality of conductive layers (11) and the semiconductor layer (51), extending in the stacking direction, and including at least one of oxygen (O) or hafnium (Hf), the insulating film (42) formed with an orthorhombic crystal structure, wherein the insulating film (42) includes a first region extending in the stacking direction along a surface of the semiconductor layer (51) on a side of the plurality of conductive layers (11), and a second region provided between the first region and the plurality of conductive layers (11) and extending in the stacking direction, the first region and the second region are separated from each other, at a plurality of first positions corresponding to the plurality of insulating layers (12) in the stacking direction, respectively, and the first region and the second region are connected at a plurality of second positions corresponding to the plurality of conductive layers (11) in the stacking direction, respectively, or a distance between the first region and the second region at the plurality of second positions is smaller than a distance between the first region and the second region at the plurality of first positions (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 16, further comprising:
a plurality of insulating members arranged along a surface of the first region on the side of the plurality of conductive layers and in the stacking direction corresponding to the plurality of insulating layers, respectively, wherein the second region extends in the stacking direction along surfaces of the first region and the plurality of insulating members on the side of the plurality of conductive layers (figures 1A and 1B; [0020-0036]).
Tokuhira teaches, in claim 20, wherein the insulating film includes a plurality of additive regions arranged in the stacking direction corresponding to the plurality of conductive layers between the first region and the second region, respectively, the additive region includes additive element selected from a group consisting of titanium (Ti), silicon (Si), and combinations thereof, and the first region and the second region do not include the additive element, or the concentration of the additive element in the first region and the second region is lower than the concentration of the additive element in the additive region (figures 1A and 1B; [0011] [0025-0026]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5, 6, 8, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tokuhira et al. (US PGPub 2020/0185395, hereinafter referred to as “Tokuhira”).
Tokuhira discloses the semiconductor device substantially as claimed. See the rejection above.
However, Tokuhira fails to explicitly teach, in claim 5, wherein a concentration of the second additive element in the first additive region is equal to or less than 6.2×10.sup.21 pieces/cm.sup.3, and a concentration of the third additive element in the second additive region is equal to or less than 6.2×10.sup.21 pieces/cm.sup.3.
Tokuhira teaches, the advantages of increasing the number of stacks and memory capacity per surface area ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective date of the claimed invention, to incorporate wherein a concentration of the second additive element in the first additive region is equal to or less than 6.2×10.sup.21 pieces/cm.sup.3, and a concentration of the third additive element in the second additive region is equal to or less than 6.2×10.sup.21 pieces/cm.sup.3., in the device of Tokuhira according to the teachings for the purpose of increasing memory capacity per square area where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Tokuhira fails to explicitly teach, in claim 6, wherein a distance between the first additive region and the second additive region is equal to or greater than 8 nm.
Tokuhira teaches, the advantages of increasing the number of stacks and memory capacity per surface area ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective date of the claimed invention, to incorporate wherein a distance between the first additive region and the second additive region is equal to or greater than 8 nm, in the device of Tokuhira according to the teachings for the purpose of increasing memory capacity per square area where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Tokuhira fails to explicitly teach, in claim 8, wherein a difference between the distance from the plurality of second portions to the semiconductor layer and the distance from the plurality of first portions to the semiconductor layer is equal to or greater than 2 nm.
Tokuhira teaches, the advantages of increasing the number of stacks and memory capacity per surface area ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective date of the claimed invention, to incorporate wherein a difference between the distance from the plurality of second portions to the semiconductor layer and the distance from the plurality of first portions to the semiconductor layer is equal to or greater than 2 nm, in the device of Tokuhira according to the teachings for the purpose of increasing memory capacity per square area where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Tokuhira fails to explicitly teach, in claim 17, wherein a first distance between the plurality of insulating members and a surface of the insulating film on a side of the semiconductor layer is equal to or less than 5 nm, and a second distance between the plurality of insulating members and a surface of the insulating film on the side of the plurality of conductive layers is equal to or less than 5 nm.
Tokuhira teaches, the advantages of increasing the number of stacks and memory capacity per surface area ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective date of the claimed invention, to incorporate wherein a first distance between the plurality of insulating members and a surface of the insulating film on a side of the semiconductor layer is equal to or less than 5 nm, and a second distance between the plurality of insulating members and a surface of the insulating film on the side of the plurality of conductive layers is equal to or less than 5 nm, in the device of Tokuhira according to the teachings for the purpose of increasing memory capacity per square area where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Tokuhira fails to explicitly teach, in claim 18, wherein a sum of the first distance and the second distance is equal to or greater than 8 nm.
Tokuhira teaches, the advantages of increasing the number of stacks and memory capacity per surface area ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective date of the claimed invention, to incorporate wherein a sum of the first distance and the second distance is equal to or greater than 8 nm, in the device of Tokuhira according to the teachings for the purpose of increasing memory capacity per square area where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Tokuhira fails to explicitly teach, in claim 19, wherein a distance between the surface of the plurality of insulating members on a side of the semiconductor layer and the surface of the plurality of insulating members on the side of the plurality of conductive layers is equal to or greater than 1 nm.
Tokuhira teaches, the advantages of increasing the number of stacks and memory capacity per surface area ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective date of the claimed invention, to incorporate wherein a distance between the surface of the plurality of insulating members on a side of the semiconductor layer and the surface of the plurality of insulating members on the side of the plurality of conductive layers is equal to or greater than 1 nm, in the device of Tokuhira according to the teachings for the purpose of increasing memory capacity per square area where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP 2144.05
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 October 3, 2026
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