DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Note
It appears that applicant has used non-black coloring to indicate changes to the claims/specification. Non-black text will be converted to lower quality, pixelated text, which is harder to read and which doesn’t lend itself to good optical character recognition (OCR). This could result in increased examining time and/or potential misprinting in the issued patent. 37 CFR 1.52(a)(1)(v) requires that papers be presented with sufficient clarity. The USPTO strongly recommends use of black-colored font (MPEP 608.01). As such, even if applicant wishes to use non-black for their own purposes, the examiner asks that applicant have a black and white version for formal submission.
For future reference, per 37 CFR 1.121, where amendments cannot be easily perceived, please use double brackets to indicate deletion. For instance, in claim 18, line 8, applicant’s strike of the comma is difficult to perceive and could be misinterpreted as a semicolon. Applicant should instead indicate deletion as [[,]].
Specification
The amended title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner recommends the title used for the parent application.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
Applicant’s amendments set forth incorrect instructions. For instance, applicant says to replace paragraph 2 on page 13 and then lists amendments to a paragraph other than paragraph 2 on page 13. Please review and fix all incorrect instructions.
Applicant has made different conflicting amendments to the exact same paragraph (incorrectly identified as being paragraph 2 on page 13), which is confusing.
Amendments to the parent disclosure made on August 1, 2019, January 3, 2020, February 1, 2021, and/or July 11, 2024, were not carried over to the instant disclosure. Please make the disclosures consistent where appropriate.
On page 1, line 22-23, it is not clear how one identified data element can occupy sequential data element positions. Wouldn’t one element occupy only one position? A similar issue exists in the paragraphs spanning p.1, line 38, to p.2, line 19.
On page 1, line 26, there is a lack of basis for “the extracted data elements” when only a single data element is extracted (which can be the case in line 22). A similar issue exists in the paragraphs spanning p.1, line 38, to p.2, line 19.
Appropriate correction is required.
A substitute specification excluding the claims is required pursuant to 37 CFR 1.125(a) due to the conflicting and confusing amendments set forth above.
A substitute specification must not contain new matter. The substitute specification must be submitted with markings showing all the changes relative to the immediate prior version of the specification of record. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived. An accompanying clean version (without markings) and a statement that the substitute specification contains no new matter must also be supplied. Numbering the paragraphs of the specification of record is not considered a change that must be shown.
Claim Objections
Claim 1 (and similarly claims 18-19) is objected to because of the following informalities:
In the 2nd to last paragraph, “a sequence consecutive data” is grammatically incorrect and must be reworded. It appears that --of-- should be inserted after “sequence”.
Claim 8 is objected to because of the following informalities:
There is a lack of basis for “the data value in each of the at least one scalar register” because no data value was necessarily previously set forth. Specifically, the at least one scalar register is not claimed as being of the one or more scalar registers that have the data values in lines 2-3. Thus, the at least one scalar register is never claimed to store a value. The examiner recommends claiming “at least one scalar register of the one or more scalar registers”.
Claim 16 is objected to because of the following informalities:
In line 3, insert --a-- before “vector output” to improve grammar.
In line 5, insert --a-- before “vector output” to improve grammar.
Claim 17 is objected to because of the following informalities:
Insert a colon after “wherein” in line 1.
Claim 18 is objected to because of the following informalities:
Delete the space before the comma in line 12.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Specifically, in claim 19:
“processing means for executing a sequence of instructions including a splice instruction” is interpreted to include vector permute unit 80, whose structure is shown in FIGs.5-7, and, optionally, one or more of arithmetic logic unit (ALU) 30, floating-point unit (FPU) 35, and load/store unit (LSU) 40, all of which are known structural components in the art. Equivalents are also encompassed.
“the processing means…for extracting from the first vector each of a sequence [of] consecutive data elements…” is interpreted to include shift/rotate circuit 220 and/or mask circuit 230, or programmable crossbar 260. Equivalents are also encompassed.
“the processing means…for outputting each extracted data element to a result vector register means” is interpreted to include OR circuit 235 and/or a bus leading to result register 245, or programmable crossbar 260 and/or a bus leading to result register 245. Equivalents are also encompassed.
“the processing means outputs…each of the plurality of extracted data elements to a plurality of consecutive sequential data element positions of the result vector register means starting from a first end of the result vector register means” is interpreted to include OR circuit 235 and/or a bus leading to result register 245, or programmable crossbar 260 and/or a bus leading to result register 245. Equivalents are also encompassed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claims 1 and 18-19, applicant claims both (i) that the at least one control register stores control data that includes location data and length data that identifies one or more data elements, and (ii) that responsive to execution of the splice instruction, irrespective of which values are specified by the location data and the length data, each of a sequence [of] consecutive data elements are extracted from the first vector. If a single data element can be identified for extraction (based on “one or more” language), then there must be some combination of values of the location and length data that identify the single element. As such, a sequence of consecutive elements will not be extracted irrespective of the values of the location and length data, because the location and length data could take on values that cause a single element to be extracted. Therefore, it is new matter to claim this combination where the control data could identify a single element for extraction but cause a sequence of consecutive elements to be extracted. If applicant believes that this is supported, please point the examiner to support.
Claims 2-17 and 20 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-8, 9-11, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 is indefinite because it is unclear how the splice instruction comprises one of at least one predicate register, but also causes a determination from the predicate data stored in said at least one predicate register, meaning it could use more than one. These seem conflicting. As previously recommended, please insert --one of said-- after “said” in claim 5, 2nd to last line.
Claims 6-7 are similarly unclear as claim 5.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 7, “the last extraction data element position” because there is such a position in claim 1, and another in claim 7. It appears that “a” should be replaced with --the-- in line 3.
In claim 8, “the data value in each of the at least one scalar register”. Lines 2-3 encompass a given scalar register storing multiple data values therein. Thus, there is no basis for “the data value” in each scalar register, because it is not clear which of potentially multiple data values in a scalar register applicant is referring to. It appears that one fix would be to claim “one or more scalar registers, each of the one or more scalar values storing a data value”.
In claim 10, “the first extraction data element position” and “the last extraction data element position”, since such positions appear previously in claim 10, but also have been introduced in claim 1. It appears that both instances of “a” in line 2 should be replaced with --the--.
In claim 11, “the data value in the identified scalar register” for similar reasoning. Again, it is not clear that there is one data value in the scalar register. Claim 8, lines 2-3 could be interpreted as each scalar register having multiple data values. As such, there is no basis for a single specific one.
In claim 18, line 10, “the location”. Please replace “the” with --a--.
Claims 6-7 and 9-11 are rejected due to their dependence on an indefinite claim.
Terminal Disclaimer
The terminal disclaimer filed on November 28, 2025, disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 12,061,906, has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding step 1 of the Subject Matter Eligibility Test, claims 1-16 and 19 are directed to a machine/apparatus, claim 18 is directed to a method/process, and claim 20 is directed to an article of manufacture.
Regarding step 2A (prong 1) of the Subject Matter Eligibility Test, claim 1 recites to extract from the first vector each of a sequence [of] consecutive data elements between the first extraction data element position and the last extraction data element position and to output each extracted data element to a result vector of data elements that also contains data elements from a second vector of data elements, and outputs, in response to extracting a plurality of extracted data elements from the first vector, irrespective of which values are specified by the location data and the length data, each of the plurality of extracted data elements to a plurality of consecutive sequential data element positions of the result vector starting from a first end of the result vector, with no intervening data element positions between the plurality of consecutive sequential data element positions. These steps fall into the grouping of mental processes (MPEP 2106.04(a)(2)(III)). Specifically, a human provided with various input data values shown in e.g. FIGs.2-4 could mentally perform, with or without the aid of pen and paper, the splice operation to generate the outputs shown in FIGs.2-4. This amounts to combining different portions of two vectors. Thus, claim 1 recites an abstract idea.
Regarding step 2A (prong 2) of the Subject Matter Eligibility Test, all remaining
elements recited by claim 1 are additional elements that do not integrate the abstract idea into a practical application (hereafter “does/do not integrate”) because they amount to mere use of an instruction (“splice instruction”) to implement the abstract idea on a computer, and a mere use of generic computer components (various registers containing input data, and circuits) to perform the abstract idea (see MPEP 2106.04(d)(I)), 6th bullet). Additionally, outputting to a result register is insignificant post-solution activity that is incidental to the claimed abstract idea and no more than a nominal or tangential addition to the claim (see MPEP 2106.04(d)(I)), 7th bullet).
Regarding step 2B of the Subject Matter Eligibility Test, the additional elements, considered alone and in combination, do not amount to significantly more than the abstract idea because the courts have determined that using an instruction and generic computer to implement the abstract idea does not amount to significantly more (see MPEP 2106.05(I)(A), second (i) and 2106.05(f)), and because storing output data to memory has been deemed by the courts to be well-understood, routine, and conventional and not significantly more (see MPEP 2106.05(I)(A) and 2106.05(d), including section II, item (iv) (“Storing…information in memory”)). Therefore, claim 1 is subject matter-ineligible under 35 U.S.C. 101 (hereafter “SMI”).
Referring to claim 2, the outputting is part of the mental process and involves a human simply taking one item from a vector and putting in at an end location of a result vector. Claiming generic processing circuitry performing this outputting does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 3, the including is part of the mental process and involves a human simply filling in the blanks of a result vector with items of a second vector. Claiming generic processing circuitry performing this including and a generic register to store input data does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 4, the including is part of the mental process and involves merely listing resulting vector elements sequentially, e.g. on paper. Claiming generic processing circuitry performing this outputting does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 5, the data used to indicate to a human how to perform the splice is claimed as being in at least one generic predicate register. Claiming such generic circuitry used by generic processing circuitry does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 6, applicant only adds more to the mental process. Thus, the claim is SMI.
Referring to claim 7, applicant adds more to the mental process by indicating what the predicate data identifies. Additionally claiming generic processing circuitry for performing the mental process does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 8, applicant claims more generic circuitry and registers to implement the abstract idea. Additionally, applicant claims storing data used in the mental process in a scalar register, which is insignificant pre-solution activity. For reasons given above, this type of claim language does not integrate or amount to significantly more. Thus, the claim is SMI.
Referring to claim 9, applicant is claiming the format of the instruction to implement the abstract idea. This is a mere instruction to implement the abstract idea. Per the Courts, this does not integrate or amount to significantly more. Thus, the claim is SMI.
Referring to claim 10, applicant adds more to the mental process by indicating what the data values in the scalar register(s) identify (so as to dictate how to control the mental splice). Additionally claiming generic processing circuitry for performing the mental process does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 11, for similar reasoning given above, where applicant only claims generic registers and storing of data therein to implement the abstract idea, there is no integration, nor is there significantly more. Thus, the claim is SMI.
Referring to claim 12, the last two lines set forth generic computing components, i.e., same size registers used in operations. Such generic processing circuitry for performing the mental process does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 13, for similar reasoning given above, where applicant only claims a generic register and storing of data therein to implement the abstract idea, there is no integration, nor is there significantly more. Thus, the claim is SMI.
Referring to claim 14, applicant claims performing iterative splicing and extracting, which can be done mentally as shown in FIG.8 based on a sequence of supplied control data. Additionally claiming generic processing circuitry including registers for performing the mental process does not integrate or amount to significantly more for reasoning set forth above. Thus, the claim is SMI.
Referring to claim 15, the shifting, generating, and analyzing steps are all part of the mental process. That is, control data from FIGs.2-4 would be analyzed, vectors would be shifted based on the analysis (FIGs.5-6), and a result would be generated (this may be done by logical OR in FIGs.5-6). A human could also mentally fill in the blanks left unoccupied by extracted elements with elements from a second vector. All circuitry claimed in claim 15 is generic in nature to perform the mental steps. Claiming such generic circuitry does not integrate or amount to significantly more. Thus, the claim is SMI.
Referring to claim 16, the masking and generation are part of the mental process. Masking is a known operation that may involve logical ANDing with 0s or 1s for instance, e.g. in FIG.6, at step 230, the data xxhgfedc could be logically ANDed with mask data 00000111 to obtain 00000edc. The AND is a mental processor or mathematical calculation. Additionally claiming mask circuitry and combination circuitry to carry out the abstract idea does not integrate or amount to significantly more. Thus, the claim is SMI.
Referring to claim 17, applicant adds programmable crossbar circuitry to generate a result vector based on control signals issues to the crossbar based on analysis of the at least one control register. A controllable crossbar switch is a generic computer component used to carry out the abstract idea and, thus, does not integrate the abstract idea into a practical application, nor does it amount to significantly more.
Claims 18-19 are rejected for similar reasoning set forth above for claim 1. Of note, the claimed means in claim 19 are merely generic components of a generic computer to implement the abstract idea.
Claim 20 is rejected for similar reasoning as claim 1. Furthermore, code on a medium is a generic part of a generic computer to implement the abstract idea. A virtual machine providing an environment is also generic.
Response to Arguments
Applicant argues the 112(b) rejection of claims 8 and 11, noting that the data in one or more scalar registers is required for the extraction.
While the examiner agrees with applicant’s description of the invention, the issue is the claim language. The main issue with claim 8 is that it’s not clear there is only one data value in each scalar register. The claim is worded such that there may be multiple data values in a given scalar register. Also, at least one scalar register is never tied to the one or more scalar registers that have the claimed data values. As such, the rejection is maintained.
On pages 13-14 of applicant’s response, applicant points out the various claimed hardware that performs the splice and then states that the claim is not a mental process but a specific definition of how hardware logic gates must operate in response to a machine code instruction. Applicant points out that a human cannot perform decoding, addressing physical vector registers, and configuring hardware circuitry.
The examiner notes that only the splice operation was mapped to a mental process (the extracting of data to create a result vector). A human, presented with a vector, can mentally extract a portion of that vector based on parameters, and place that portion into a new result vector. The hardware involved in this process was identified, not as part of the abstract idea, but to include additional elements, which are nothing more than generic computing components to perform the mental process. There is also recitation of a mere instruction to perform the mental process on a generic computer.
On page 14 of applicant’s response, applicant argues that the instruction is vector length agnostic, and, thus, provides an improvement, as it allows software to be written for different hardware implementations without needed to be re-compiled or re-coded for different vector register sizes.
Per MPEP 2106.05(a), the claim itself must reflect the disclosed improvement in technology. The examiner does not see the improvement reflected. The claim, under BRI, is directed to generic control of vector registers of a single size.
On page 14, applicant argues that the claim is not directed to a generic computer, but to special processing circuitry capable of interpreting the specific instruction to perform the specific splice.
The examiner respectfully disagrees. Nothing but generic computer components are claimed (vector registers, control registers, processing circuitry, result register). These are generic and, thus, do not integrate the splice into a practical application or amount to significantly more.
On page 16 of applicant’s response, applicant argues that Fridman does not describe extracting all elements between the first and last extraction points irrespective of the values of the location and length data
The examiner generally agrees because Fridman can extract just one element when there is only one bit set in the mask. In such a case, each of a sequence of multiple consecutive elements between the first and last extraction points would not be extracted. However, the examiner notes the 112(a) issue with the claims. Should applicant overcome the 112(a) issue, a rejection based on Fridman would be reconsidered.
Applicant makes a similar argument with respect to Corbal on pp.16-17 of the response. The examiner’s response is similar to that above.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Spracklen, 2003/0221089, has taught that a programmable crossbar switch (FIG.3C, 400, and FIG.5), which can shift any input to any output in response to control inputs 320, is well known in the art (paragraphs 60-72).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183