DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 03 July 2024. The information therein was considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,538,862 (‘862). Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application are recited in the claims of ‘862 with only nominal differences that would have been obvious to one of ordinary skill in the art.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,069,871 (‘871). Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application are recited in the claims of ‘871 with only nominal differences that would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 1-20 would be allowable if the double patenting rejection set forth in this Office action is overcome.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, a memory device, comprising: a first insulating layer; a stacking layer overlying the first insulating layer and comprising a gate layer, a semiconductor layer, and a gate dielectric layer that are laterally stacked; a second insulating layer overlying the stacking layer; a memory structure bordering the semiconductor layer; and a conductive structure bordering the semiconductor layer and laterally spaced from the memory structure; wherein the memory and conductive structures have individual heights greater than a combined height of the first and second insulating layers and the stacking layer; and as recited in independent claim 8, a memory device, comprising: a first stacking layer comprising a first gate layer, a first channel layer, and a first gate dielectric layer laterally between the first gate layer and the first channel layer; a second stacking layer overlying the first stacking layer and comprising a second gate layer, a second channel layer, and a second gate dielectric layer laterally between the second gate layer and the second channel layer; a conductive pillar bordering the first and second channel layers; and a memory pillar bordering the first and second channel layers and laterally spaced from the conductive pillar, wherein the memory pillar comprises a switching layer; and as recited in independent claim 16, a method for forming a memory device, wherein the method comprises: forming a multilayer stack comprising a sacrificial layer; performing an etch into the multilayer stack to form a trench; forming a channel layer recessed into a sidewall of the multilayer stack at the sacrificial layer, wherein the sidewall is in the trench; forming a memory pillar and a conductive pillar bordering the channel layer, wherein the memory pillar comprises a switching layer; and replacing the sacrificial layer with a gate layer after the forming of the memory pillar and the conductive pillar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han US 11,508,741 teaches a memory device including a bit line structure and a resistance change structure contacting different portions of a channel layer.
Chen US 11,785,869 teaches a memory device including a stack structure including channel layers embedded in conductive layers; a source line penetrating the stack structure to be electrically connected to first sides of the channel layers; and switching layers wrapped around bit lines to contact second sides of the channel layers.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 10/1/2026
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