DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-8, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koo (US 6,236,588) in view of Choi et al. (US 6,055,200 “Choi”).
Regarding claim 1, Koo discloses a method, comprising:
performing operation (sensing a voltage difference to determine logical data values; fig. 1, 4) on data values (logical values “1” or “0”; column/line(s): 1/64-67, 2/1-23) respectively stored in a first memory cell (102; fig. 3) and a second memory cell (charge dump ferroelectric capacitor 105 having polarization state corresponding to a logical data, considered equivalent to a memory cell that stores logical data; column/line(s): 1/17-24, 9/8-11) coupled to a first digit line (BL1T/2T; fig. 3) to which a sense amplifier (S/A; fig. 3) is coupled by:
activating (switching to a “H” level; fig. 4):
a first word line (WLiT; fig. 3) coupled to the first memory cell (102);
a second word line (AWLT; fig. 3) coupled to the second memory cell (105); and
a third word line (RWLB; fig. 3) coupled to a third memory cell (111; fig. 3), wherein the third memory cell is coupled to a second digit line (BL1B/2B; fig. 3) to which the sense amplifier (S/A) is coupled; and
activating the sense amplifier (S/A activated for the sensing; column/line(s): 8/51-54), wherein a data value sensed (sensing data value stored in memory cells; column/line(s): 1/65) at the sense amplifier corresponds to a result of the operation (the data value having the logical value “1”/“0” is a result of the logical operation, i.e. in determining the data value).
Koo does not expressly disclose a logical [operation].
Choi discloses a logical operation (signal generating circuit(s) 30, 40, and sense amplifier SA comprises transistors configured for logical operations; fig. 2A/2B-4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Regarding claim 2, Koo discloses the method of claim 1, wherein the third memory cell is configured to store a first reference data value or a second reference data value (fig. 1, further column/line(s): 7/64-67, 8/1-5).
Regarding claim 6, Koo method of claim 1, further comprising concurrently activating the first, second, and third word lines (fig. 4).
Regarding claim 7, Koo discloses an apparatus, comprising:
a first digit line (BL1T/2T; fig. 3) coupled to a first plurality of memory cells (memory cells of array 12, memory cells 102; fig. 3, and further charge dump ferroelectric capacitors 105 having polarization state corresponding to a logical data, considered equivalent to memory cells that stores logical data; column/line(s): 1/17-24, 9/8-11), the first plurality of memory cells being coupled to respective first word lines (RWLT, WLiT, AWLT; fig. 3);
a second digit line (BL1B/2B; fig. 3) coupled to a second plurality of memory cells (memory cells 111, memory cells of array 20; fig. 3, and further charge dump ferroelectric capacitors 115 having polarization state corresponding to a logical data, considered equivalent to memory cells that stores logical data; column/line(s): 1/17-24, 9/8-11), the second plurality of memory cells being coupled to respective second word lines (RWLB, WLiB, AWLB; fig. 3);
a sense amplifier (S/A; fig. 3) coupled to the first digit line (BL1T/2T) and to the second digit line (BL1B/2B); and
a controller (any circuit for providing control signals; fig. 3-4) configured to perform operation (sensing a voltage difference to determine logical data values; fig. 1, 4) on data values (logical values “1” or “0”; column/line(s): 1/64-67, 2/1-23) stored in at least two of the first plurality of memory cells (102, 105) by:
activating (switching to a “H” level; fig. 4) corresponding first word lines (WLiT, AWLT) to which the at least two memory cells (102, 105) are coupled;
activating (switching to a “H” level; fig. 4) a corresponding second word line (RWLB) to which a memory cell (111) of the second plurality of memory cells is coupled, wherein the memory cell of the second plurality stores a voltage (fig. 1) corresponding to a reference data value (fig. 1, further column/line(s): 7/64-67, 8/1-5); and
activating the sense amplifier (S/A activated for the sensing; column/line(s): 8/51-54) to store a result of the operation therein (the data value having the logical value “1”/“0” is a result of the logical operation, i.e. in determining the data value).
Koo does not expressly disclose a logical [operation].
Choi discloses a logical operation (signal generating circuit(s) 30, 40, and sense amplifier SA comprises transistors configured for logical operations; fig. 2A/2B-4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Regarding claim 8, Koo discloses the apparatus of claim 7, wherein the controller is configured to concurrently activate the corresponding first word lines to which the at least two memory cells are coupled and the corresponding second word line to which the memory cell of the second plurality of memory cells is coupled (fig. 4).
Regarding claim 10, Koo discloses the apparatus of claim 7, wherein the result of the operation is one of: a first data value responsive to the reference data value being a first reference data value; or a second data value responsive to the reference data value being a second reference data value (column/line(s): 2/57-67, 3/1-2, 9/56-67, 8/1-25).
Koo does not expressly disclose the logical [operation].
Choi discloses a logical operation (signal generating circuit(s) 30, 40, and sense amplifier SA comprises transistors configured for logical operations; fig. 2A/2B-4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Claim(s) 5, 9, 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koo (US 6,236,588) in view of Choi et al. (US 6,055,200 “Choi”), and further in view of Hsu et al. (US. 2003/0081447 “Hsu”).
Regarding claim 5, Koo discloses the method of claim 1, further comprising: equilibrating the first, second, and third word lines prior to activating the first, second, and third word lines; and while the first, second, and third word lines are activated (fig. 4).
Koo, as modified, does not expressly disclose activating the sense amplifier [while the first, second, and third word lines are activated].
Hsu discloses activating sense amplifier while word lines are activated (fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is further modifiable as taught by Hsu for the purpose of facilitating data accessing schemes by enhancing signals to achieve optimal voltage margins, which further improves data retention time (para 0043 of Hsu).
Regarding claim 9, Koo discloses the apparatus of claim 8, wherein the controller is configured to activate the corresponding first word lines to which the at least two memory cells are coupled and the corresponding second word line to which the memory cell of the second plurality of memory cells is coupled are concurrently activated (fig. 4).
Koo, as modified, does not expressly disclose activate the sense amplifier while [word lines are activated].
Hsu discloses activating sense amplifier while word lines are activated (fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is further modifiable as taught by Hsu for the purpose of facilitating data accessing schemes by enhancing signals to achieve optimal voltage margins, which further improves data retention time (para 0043 of Hsu).
Regarding claim 13, Hsu discloses the apparatus of claim 7, wherein the apparatus comprises a dynamic random access memory (DRAM) device (para 0017).
Hsu discloses activating sense amplifier while word lines are activated (fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is further modifiable as taught by Hsu for the purpose of facilitating data accessing schemes by enhancing signals to achieve optimal voltage margins, which further improves data retention time applicable to any data storage (para 0043, 0058 of Hsu).
Regarding claim 14, Koo discloses an apparatus, comprising:
a memory array comprising:
a plurality of memory cells (memory cells of array 12, memory cells 102; fig. 3, and further charge dump ferroelectric capacitors 105 having polarization state corresponding to a logical data, considered equivalent to memory cells that stores logical data; column/line(s): 1/17-24, 9/8-11) coupled to a first digit line (BL1T/2T; fig. 3);
a first memory cell (111; fig. 3) coupled to a second digit line (BL1B/2B; fig. 3) and a first word line (RWLB; fig. 3), the first memory cell configured to store a first reference data value having a first data value (fig. 1, further column/line(s): 7/64-67, 8/1-5);
a second memory cell (another of 111; fig. 3) coupled to the second digit line (BL1B/2B), the second memory cell configured store a second reference data value having a second data value (fig. 1, further column/line(s): 7/64-67, 8/1-5); and
a sense amplifier(S/A; fig. 3) coupled to the first (BL1T/2T) and second (BL1B/2B) digit lines; and
a controller (any circuit for providing control signals; fig. 3-4) is configured to, in order to perform a first operation (sensing a voltage difference to determine logical data values; fig. 1, 4) on data values (logical values “1” or “0”; column/line(s): 1/64-67, 2/1-23) respectively stored in two memory cells (102, 105) of the plurality of memory cells coupled to the first digit line (BL1T/2T):
activate (switching to a “H” level; fig. 4) two word lines (WLiT, AWLT; fig. 3) coupled to the two memory cells (102, 105); and
activate (switching to a “H” level; fig. 4), substantially concurrently with the two word lines being activated, the first word line (RWLB) to further adjust a voltage differential (a voltage difference sensed by the sense amplifier is adjusted based on adjusting bit line voltage(s); column/line(s): 2/57-67, 3/1-2) sensed at the sense amplifier (S/A) based on the first reference data value stored (i.e. based on comparing the first reference data value stored in first memory cell 111, as reflected on BL1B/2B, with BL1T/2T) on the first memory cell (column/line(s): 8/51-54).
Koo does not expressly disclose a logical [operation]; [a second memory cell coupled to the second digit line] and a second word line.
Choi discloses a logical operation (signal generating circuit(s) 30, 40, and sense amplifier SA comprises transistors configured for logical operations; fig. 2A/2B-4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Hsu discloses a second word line (a second reference word line RWL2, i.e. a second memory cell coupled to a second digit line BL1/bBL1 and second reference word line RWL2; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is further modifiable as taught by Hsu since it is common and well known in the prior art to have multiple reference word lines in which predictable results are identified with a reasonable expectation of success, and further to facilitating data accessing schemes by maintaining optimal biasing (para 0017-0021 of Hsu).
Regarding claim 15, Koo discloses the apparatus of claim 14, wherein the controller is configured to, in order to perform a second operation on data values respectively stored in two memory cells of the plurality of memory cells coupled to the first digit line:
activate two word lines coupled to the two memory cells; and
activate, substantially concurrently with the two word lines being activated, to further adjust a voltage differential sensed at the sense amplifier based on the second reference data value stored on the second memory cell (fig. 4).
Koo, as modified, does not expressly disclose activate the second word line.
Hsu discloses activate (i.e. for sensing) second word line (a second reference word line RWL2, i.e. a second memory cell coupled to a second digit line BL1/bBL1 and second reference word line RWL2; fig. 1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is further modifiable as taught by Hsu since it is common and well known in the prior art to have multiple reference word lines in which predictable results are identified with a reasonable expectation of success, and further to facilitating data accessing schemes by maintaining optimal biasing (para 0017-0021 of Hsu).
Regarding claim 16, Koo discloses the apparatus of claim 14, wherein the activation of the first word line coupled to the first memory cell storing the first reference data value increases a voltage level at which the second digit line is biased (biasing based on adjusting a voltage level of digit line(s); column/line(s): 2/57-67, 3/1-2).
Regarding claim 17, Choi discloses the apparatus of claim 16, wherein the first logical operation is an AND logical operation (fig. 2A/2B, 3, 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Regarding claim 18, Koo discloses the apparatus of claim 14, wherein the activation of the second word line coupled to the first memory cell storing the first reference data value decreases a voltage level at which the second digit line is biased (biasing based on adjusting a voltage level of digit line(s); column/line(s): 2/57-67, 3/1-2).
Regarding claim 19, Choi discloses the apparatus of claim 17, wherein the first logical operation is an OR logical operation (fig. 2A/2B, 3, 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Regarding claim 20, Choi discloses the apparatus of claim 14, wherein the sense amplifier is one of plurality sense amplifiers, and wherein the controller is configured to perform a plurality of logical operation substantially concurrently using the plurality of sense amplifiers (fig. 2A/2B, 3, 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Koo is modifiable as taught by Choi for the purpose of facilitating data accessing schemes by providing operational signals to improve the reliability of the device (column/line(s): 8/55+ of Choi).
Allowable Subject Matter
Claim(s) 3-4, 11-12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 3, the prior art fails to teach or suggest the claimed limitations, namely performing a logical AND operation on the data values respectively stored in the first memory cell and the second memory cell responsive to the third memory cell storing the first reference data value.
With respect to dependent claim 4, the prior art fails to teach or suggest the claimed limitations, namely performing a logical OR operation on the data values respectively stored in the first memory cell and the second memory cell responsive to the third memory cell storing the second data value.
With respect to dependent claim 11 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely the result of the logical operation is a logical AND result responsive to the reference data value being the first data value; and the result of the logical operation is a logical OR result responsive to the reference data value being the second data value.
The allowable claims are supported in at least fig. 2 of the instant application.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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