DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. PGPub 2022/0037328).
Regarding claim 1, Kim teaches a semiconductor device (Fig. 18), comprising:
a substrate (100, [0016]),
an active pattern on the substrate ([0141]), and
a word line structure crossing the active pattern (Fig. 1, gate structure, [0143]-[0145]),
wherein the word line structure includes
a word line (112, 114, 116a, [0025]-[0026]),
a capping pattern on the word line (120, [0043]), and
a protection insulating pattern between the word line and the capping pattern (118, [0045], [0034]).
Regarding claim 2, Kim teaches wherein the word line comprises a first conductive pattern and a second conductive pattern, the second conductive pattern is between the first conductive pattern and the protection insulating pattern, and the second conductive pattern is in contact with the protection insulating pattern (first conductive pattern 112/114, second conductive pattern 116a, [0024]-[0028]).
Regarding claim 3, Kim teaches wherein the second conductive pattern is spaced apart from the capping pattern, and the protection insulating pattern is between the second conductive pattern and the capping pattern (Fig. 1).
Regarding claim 4, Kim teaches wherein the first conductive pattern comprises both a metallic material and a separate nitride material, the separate nitride material a nitride of the metallic material (112, 114, [0025]),
the metal material comprises at least one of titanium (Ti), molybdenum (Mo), tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), ruthenium (Ru), or iridium (Ir) (tungsten, aluminum, copper, [0023], [0025]),
the second conductive pattern comprises doped poly silicon ([0028]), and
the protection insulating pattern comprises silicon oxide, ([0034]).
Regarding claim 5, Kim teaches a gate insulating pattern extended into a region between the active pattern and the word line, wherein the protection insulating pattern is in contact with the gate insulating pattern (Fig. 1, 106, [0018]).
Regarding claim 6, Kim teaches a device isolation layer enclosing the active pattern, wherein the gate insulating pattern is between the device isolation layer and the protection insulating pattern, and the gate insulating pattern is between the active pattern and the protection insulating pattern (Fig. 18, 142, [0141]).
Regarding claim 7, Kim teaches a semiconductor device (Fig. 18), comprising:
a substrate (100, [0016]),
a device isolation pattern on the substrate (Fig. 18, 142, [0141]),
an active pattern on the substrate, the active pattern enclosed by the device isolation pattern ([0141]), and
a word line structure crossing the device isolation pattern and the active pattern in a first direction, the first direction parallel to a top surface of the substrate (Figs. 1, 18, gate structure, [0143]-[0145]),
wherein the word line structure includes
a word line (112, 114, 116a, [0025]-[0026]),
a capping pattern on the word line (120, [0043]), and
a protection insulating pattern on the word line, the protection insulating pattern enclosing bottom and side surfaces of the capping pattern (118, [0045], [0034]).
wherein the word line has a first width in a second direction, the second direction parallel to the top surface of the substrate and perpendicular to the first direction, wherein a bottom surface of the capping pattern has a second width in the second direction, and wherein the second width is smaller than the first width (Fig. 1).
Regarding claim 10, Kim teaches a buffer pattern covering each of the active pattern, the device isolation pattern, and the word line, wherein the buffer pattern is in contact with the protection insulating pattern (410, [0147]-[0148]).
Regarding claim 11, Kim teaches a gate insulating pattern extended into a space between the active pattern and the word line, wherein a level of a top surface of the protection insulating pattern is equal to a level of a top surface of the gate insulating pattern (Fig. 1, 106, [0018]).
Regarding claim 12, Kim teaches wherein the protection insulating pattern is between the gate insulating pattern and the capping pattern (Fig. 1).
Regarding claim 13, Kim teaches wherein the gate insulating pattern and the protection insulating pattern each comprise silicon oxide ([0018], [0034]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PGPub 2022/0037328).
Regarding claim 8, Kim does not explicitly teach wherein a thickness of the protection insulating pattern is 5% to 40% of a length of the first width.
Kim teaches wherein the thickness of the protection insulating pattern controls the decrease of gate-induced drain leakage ([0037]-[0039]). Therefore, the thickness is a result-effective variable. Mere optimization of a result effective variable is prima facie obvious. See MPEP 2144.05IIB.
Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Kim such that a thickness of the protection insulating pattern is 5% to 40% of a length of the first width for the purpose of optimizing the decrease of gate-induced drain leakage.
Regarding claim 9, Kim teaches wherein a length of the first width is equal to a sum of a length of the second width and two times the thickness of the protection insulating pattern (Fig. 1).
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PGPub 2022/0037328) in view of Song (U.S. PGPub 2019/0164975).
Regarding claim 14, Kim teaches a semiconductor device (Fig. 18), comprising:
a substrate (100, [0016]),
a device isolation pattern on the substrate (Fig. 18, 142, [0141]),
an active pattern on the substrate, the active pattern enclosed by the device isolation pattern ([0141]), and
a word line structure extending in a first direction parallel to a top surface of the substrate (Fig. 1, gate structure, [0143]-[0145]),
a bit line on the active pattern and extended in a second direction crossing the first direction (430, [0151]),
a capacitor (442, [0155]),
wherein the word line structure includes
a first conductive pattern (112/114, [0024]-[0025]),
a second conductive pattern on the first conductive pattern (116a, [0026]-[0028]),
a capping pattern on the second conductive pattern (120, [0043]), and
a protection insulating pattern between the second conductive pattern and the capping pattern (118, [0045], [0034]).
wherein the protection insulating pattern includes a first vertical portion, a second vertical portion, and a horizontal portion connecting the first vertical portion to the second vertical portion,
wherein the first and second vertical portions are each in contact with a side surface of the capping pattern, and
wherein the horizontal portion is in contact with a bottom surface of the capping pattern (Fig. 1).
Kim does not explicitly teach the word line structure crossing the active pattern and the device isolation pattern, a bit line contact between the active pattern and the bit line, a storage node contact on the active pattern, a landing pad on the storage node contact, and a capacitor on the landing pad.
Song teaches a memory device comprising a substrate (100), a device isolation pattern on the substrate (102), a word line structure extended in a first direction and crossing the active pattern and the device isolation pattern (WL, Fig. 2), a bit line on the active pattern and extended in a second direction crossing the first direction (BL, Fig. 2), a bit line contact between the active pattern and the bit line (DC, [0028]), a storage node contact on the active pattern (BC, [0030]), a landing pad on the storage node contact (LP, [0032]-[0033]), and a capacitor on the landing pad ([0037]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Song with Kim such that the word line structure crosses the active pattern and the device isolation pattern, a bit line contact between the active pattern and the bit line, a storage node contact on the active pattern, a landing pad on the storage node contact, and a capacitor on the landing pad for the purpose of providing a device with for high integration and improved process margins and reliability (Song, [0038], [0065]) with reduced leakage current (Kim, [0158], [0161]).
Regarding claim 15, the combination of Kim and Song teaches a gate insulating pattern extended into a space between the active pattern and the word line structure, wherein the first and second vertical portions of the protection insulating pattern are between the gate insulating pattern and the capping pattern (Kim, Fig. 1, 106, [0018]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim and Song for the reasons set forth in the rejection of claim 14.
Regarding claim 16, the combination of Kim and Song teaches wherein top surfaces of the first and second vertical portions of the protection insulating pattern are at a same level as a top surface of the capping pattern (Kim, Fig. 1). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim and Song for the reasons set forth in the rejection of claim 14.
Regarding claim 17, the combination of Kim and Song teaches wherein the horizontal portion of the protection insulating pattern is between the second conductive pattern and the capping pattern (Kim, Fig. 1). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim and Song for the reasons set forth in the rejection of claim 14.
Regarding claim 18, the combination of Kim and Song teaches wherein the second conductive pattern is between the first conductive pattern and the horizontal portion of the protection insulating pattern (Kim, Fig. 1). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim and Song for the reasons set forth in the rejection of claim 14.
Regarding claim 19, the combination of Kim and Song teaches wherein a bottom surface of the horizontal portion of the protection insulating pattern is in contact with a top surface of the second conductive pattern (Kim, Fig. 1). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim and Song for the reasons set forth in the rejection of claim 14.
Regarding claim 20, the combination of Kim and Song teaches wherein a sum of a thickness of the protection insulating pattern in the second direction and a thickness of a first portion of the gate insulating pattern that is above a word line of the word line structure in the second direction is larger than a thickness of a second portion of the gate insulating pattern that is below the protection insulating pattern, in the second direction (Kim, [0019], the gate insulating layer has a uniform thickness, therefore the sum of the thickness of the gate insulating layer and another layer is greater than the thickness of the gate insulating layer). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Kim and Song for the reasons set forth in the rejection of claim 14.
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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