Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 3, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 15, 17
b. Pending: 1-20
Claim Objections
Claims 3, 6, 9, 10, 16, 19, and 20 are objected to because of the following informality: all of the above claims include instances of the phrase “number of” without the article “a” or “the” preceding it. For example, make the following change to claim 3: “the control circuit is configured to set the voltage offset based on a number of program-erase cycles performed by the non-volatile storage apparatus.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 12-14 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cho et al. (US Pub20230253057 A1; “Cho”).
Regarding independent claim 1, Cho discloses a non-volatile storage apparatus (Fig. 1: nonvolatile memory device 100; [0028]), comprising:
a first plurality of non-volatile memory cells (memory cell array 110; [0028]); and
a control circuit connected to the first plurality of non-volatile memory cells (control logic block 170; [0028]), the control circuit is configured to:
start a programming process for the first plurality of non-volatile memory cells ([0043]: FIG. 2 illustrates an example in which a program operation is performed) that includes applying program voltage pulses to the first plurality of non-volatile memory cells that increase in voltage magnitude from pulse to pulse ([0050]: The program operation may be performed by repeating program loops. When a program loop progresses (is repeated), a level of the program voltage VPGM may increase as much as a first voltage ΔV1),
suspend the programming process prior to completing the programming process (Fig. 4: operation S120; [0076]),
perform a different task other than programming while the programming process is suspended ([0051]: The nonvolatile memory device 100 according to example embodiments of the inventive concepts may support a function of suspending and resuming the program operation such that an urgent access is performed while performing the program operation. Examiner notes that operations S130 and the S140 ‘no’ loop are also analogous to task other than programming), and
after starting the different task, resume the programming process (S140/S150; [0077]: When the resume command is received, the nonvolatile memory device 100 may perform operation S150) including setting a magnitude of a next program voltage pulse based on amount of usage of the non-volatile storage apparatus ([0085]: the second voltage ΔV2 may be further adjusted based on at least one of the number of program loops already performed, a level of the program voltage VPGM finally applied, and information of states completely programmed from among program states. Also see Fig. 5).
Regarding claim 2, Cho discloses the limitations of claim 1. Further, wherein:
the control circuit is configured to perform the programming process for the first plurality of non-volatile memory cells by applying program voltage pulses that increase in voltage magnitude from pulse to pulse by a nominal increment (Fig. 2; [0043]; [0050]);
the control circuit is further configured to set a voltage offset based on amount of usage of the non-volatile storage apparatus ([0085]); and
the control circuit is configured to set the magnitude of the next program voltage pulse based on amount of usage of the non-volatile storage apparatus by setting the magnitude of the next program voltage pulse to a voltage magnitude of a previous program voltage pulse ([0084]: After the program operation is resumed, when the program voltage VPGM is secondly applied, the increment of the program voltage VPGM may be returned to the first voltage ΔV1. That is, when the program loop is performed, the program voltage VPGM may increase from a previous level as much as the first voltage ΔV1) plus the nominal increment adjusted by the voltage offset ([0085]).
Regarding claim 3, Cho discloses the limitations of claim 2. Further, wherein:
the control circuit is configured to set the voltage offset based on number of program-erase cycles performed by the non-volatile storage apparatus ([0087]: the second voltage ΔV2 may be further adjusted based on external information, which is provided from the external device, such as the number of program and erase cycles associated with selected memory cells).
Regarding claim 4, Cho discloses the limitations of claim 2. Further, wherein:
the control circuit is configured to set the voltage offset to a first value in response to the number of program-erase cycles performed by the non-volatile storage apparatus being in a first range;
the control circuit is configured to set the voltage offset to a second value in response to the number of program-erase cycles performed by the non-volatile storage apparatus being in a second range, the first range is different than the second range;
the control circuit is configured to set the voltage offset to a third value in response to the number of program-erase cycles performed by the non-volatile storage apparatus being in a third range, the first range is different than the third range, the second range is different than the third range;
the first range is lower than the second range;
the second range is lower than the third range;
the first voltage offset is greater in magnitude than the second voltage offset; and
the second voltage offset is greater in magnitude than the third voltage offset ([0085]; [0078]: In operation S150, the nonvolatile memory device 100 may adjust a voltage of the program operation based on the resume time tRES. For example, the nonvolatile memory device 100 may adjust the program voltage VPGM based on the resume time tRES. The table 172 may store information of a second voltage ΔV2 corresponding to the resume time tRES. The nonvolatile memory device 100 may adjust the second voltage ΔV2 with reference to the table 172. A person with ordinary skill in the art would know that if a voltage offset depends on a count, it follows that offsets of different amounts may correspond to different offset ranges. Examiner also points to the description of the table 172. Per [0082] and [0085], the offset may be changed based on the program cycle count in addition to the resume time tRES. Both are parameters that may be included in the table 172 that indicates offset level).
Regarding claim 12, Cho discloses the limitations of claim 1. Further, wherein:
the control circuit is configured to suspend the programming process after applying a program voltage pulse and before starting a verify operation ([0056]: In response to the first request R1, the nonvolatile memory device 100 may start a first operation, that is, the program operation. Because the nonvolatile memory device 100 supports the function of suspending and resuming the program operation, the nonvolatile memory device 100 may start the first operation and may set the ready/busy signal RnB to the ready state; [0057]: Before the first operation is completed, the nonvolatile memory device 100 may receive a second request R2 from the external device. The second request R2 may include a second command CMD2. The second command CMD2 may be a suspend command).
Regarding claim 13, Cho discloses the limitations of claim 1. Further, wherein:
the control circuit is configured to suspend the programming process between verify operations scheduled to be performed before a next program voltage pulse ([0058]: The suspend operation SUS may include storing (or backing up) progress information of the first operation. The progress information of the first operation may include data (e.g., program progress data) updated (or obtained) by applying a verification result of a program operation of selected memory cells to the first data DATA1 loaded to the page buffer block 130).
Regarding claim 14, Cho discloses the limitations of claim 1. Further, wherein:
the control circuit is configured to suspend the programming process after all verify operations scheduled to be performed before a next program voltage pulse ([0058]: The suspend operation SUS may include storing (or backing up) progress information of the first operation; [0059]: The progress information of the first operation may further include the number of program loops already performed, a level of the program voltage VPGM finally applied, and information of states completely programmed from among program states. The progress information of the first operation may further include information of an interval, in which the suspend operation SUS is performed, from among the bit line setup interval I_BLS, the program interval I_PGM, and the verify interval I_VFY of a program loop).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US Pub20230253057 A1) as applied to claim 1 above and further in view of Harada et al. (US Pub. 20210335433 A1; “Harada”).
Regarding claim 5, Cho discloses the limitations of claim 1. The first two limitations of claim 5 are identical to the first two limitations of claim 2, and the third limitation of claim 5 is mostly identical to the third limitation of claim 2, so these limitations are thus rejected for the same reasons. Cho does not fully disclose:
the control circuit is configured to set the magnitude of the next program voltage pulse by setting the magnitude of the next program voltage pulse to a voltage magnitude of a previous program voltage pulse plus the nominal increment adjusted by the voltage offset in response to the programming process being suspended for greater than the first time period.
However, Harada teaches:
the control circuit (Fig. 1: memory controller 200; [0032]) is configured to set the magnitude of the next program voltage pulse by setting the magnitude of the next program voltage pulse (Fig. 14B after time t3) to a voltage magnitude of a previous program voltage pulse (program pulse right before time t1) plus the nominal increment (predetermined amount of increase DVPGM1; [0090]) adjusted by the voltage offset (amount of increase DVPGM2; [0108]) in response to the programming process being suspended for greater than the first time period (period D>Dth; see [0143]-[0144]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Harada to Cho wherein the control circuit is configured to set the magnitude of the next program voltage pulse by setting the magnitude of the next program voltage pulse to a voltage magnitude of a previous program voltage pulse plus the nominal increment adjusted by the voltage offset in response to the programming process being suspended for greater than the first time period in order to perform an interrupt operation without deteriorating performance of a write operation (Harada, [0115]).
Regarding claim 6, Cho and Harada together disclose the limitations of
claim 5. Claim 6 recites exactly the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 7, Cho discloses the limitations of claim 1. The first two limitations and most of the third limitation of Claim 7 are nearly identical to the limitations of claim 5, so these limitations are thus rejected for the same reasons. Cho does not fully disclose:
and setting the magnitude of the next program voltage pulse to the voltage magnitude of the previous program voltage pulse plus the nominal increment in response to the programming process being suspended for less than the first time period.
However, Harada teaches:
and setting the magnitude of the next program voltage pulse (Fig. 14A after time t2) to the voltage magnitude of the previous program voltage pulse plus the nominal increment in response to the programming process being suspended for less than the first time period (period D<Dth; [0146]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Harada to modified Cho wherein the control circuit is configured to set magnitude of the next program voltage pulse to the voltage magnitude of the previous program voltage pulse plus the nominal increment in response to the programming process being suspended for less than the first time period in order to perform an interrupt operation without deteriorating performance of a write operation (Harada, [0115]).
Regarding claim 8, Cho and Harada together disclose the limitations of
claim 7. Further, through Harada:
the control circuit is configured to set the duration of the first time period based on amount of usage of the non-volatile storage apparatus ([0143]: The threshold Dth corresponds to, for example, a period until the threshold voltage of the memory cell transistor MT that was increased by the program operation, decreases due to the lapse of time. Examiner asserts that time lapse could be an indicator of usage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Harada to modified Cho wherein the control circuit is configured to set the duration of the first time period based on amount of usage of the non-volatile storage apparatus in order to perform an interrupt operation without deteriorating performance of a write operation (Harada, [0115]).
Regarding claim 9, Cho and Harada together disclose the limitations of
claim 7. Further, through Harada:
the control circuit is configured to set the duration of the first time period based on number of program-erase cycles performed by the non-volatile storage apparatus (Examiner asserts that a person with ordinary skill in the art would know that a number of program-erase cycles is an indicator of usage (see end of para. [0039] of the Specification of the present application) and therefore is another reasonable example of what Dth in para. [0143] of Harada could correspond to.
Regarding claim 10, Cho and Harada together disclose the limitations of
claim 7. The first limitation of claim 10 is exactly the same as claim 3, and the second limitation of claim 10 is exactly the same as claim 9. Thus, claim 10 is rejected for the same reasons as claims 3 and 9.
Regarding claim 11, Cho discloses the limitations of claim 1. The first limitation of claim 11 is substantially the same as the last limitation of claim 5, and the second limitation of claim 10 is exactly the same as claim 8. Thus, claim 10 is rejected for the same reasons as claims 5 and 8.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US Pub20230253057 A1) in view of Harada (US Pub. 20210335433 A1).
Independent claim 15 has a first and second limitation that are exactly the same as the first two limitations of claim 1, a third limitation that is exactly the same as claim 8, fourth through sixth limitations that are substantially the same as the third through fifth limitations of claim 1, and a seventh limitation that is substantially the same as the last limitation of claim 7. Thus, independent claim 15 is rejected for the same reasons as those other claims.
Regarding claim 16, Cho and Harada together disclose the limitations of
claim 15. Claim 16 recites exactly the same limitations as claim 9, and henceforth is rejected for the same reasons.
Independent claim 17 has a first limitation that is exactly the same as claim 8, a second limitation that is exactly the same as same as the second limitation of claim 2, a third limitation that is exactly the same as the first limitation of claim 2, fourth and fifth limitations that are exactly the same as the fourth and fifth limitations of claim 1, a sixth limitation that is substantially the same as the last limitation of claim 5, and a seventh limitation that is substantially the same as the last limitation of claim 7. Thus, independent claim 17 is rejected for the same reasons as those other claims.
Regarding claim 18, Cho and Harada together disclose the limitations of
claim 17. Further, through Harada:
the resuming the programming process is performed after completing the different task ([0138]: in the example of FIG. 12B, the write operation is interrupted within the period D. In this case, the verification operation in the second program loop is not executed until the interrupt operation has completed after the immediately preceding program operation has completed).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Harada to modified Cho wherein the resuming the programming process is performed after completing the different task in order to perform an interrupt operation without deteriorating performance of a write operation (Harada, [0115]).
Regarding claim 19, Cho and Harada together disclose the limitations of claim 17. The first limitation of claim 19 is substantially the same as claim 9, and the second limitation of claim 19 is substantially the same as claim 3. Thus, claim 19 is rejected for the same reasons as claims 9 and 3.
Regarding claim 20, Cho and Harada together disclose the limitations of claim 17. The limitations of claim 20 are substantially the same as claim 9 and claim 3. Further, through Harada:
the first time period is set to be longer as the number of program-erase cycles increases ([0143]: The threshold Dth corresponds to, for example, a period until the threshold voltage of the memory cell transistor MT that was increased by the program operation, decreases due to the lapse of time. Examiner asserts that the period until the threshold voltage of MT decreases is longer if there were more programming loops); and
the voltage offset is set to be smaller as the number of program-erase cycles increases ([0108]: In step ST90, the sequencer 170 changes an amount of increase in the program voltage VPGM in the program operation up to the n-th time after the write operation is resumed from DVPGM1 to DVPGM2 (the number n is an integer of 1 or more). The amount of increase DVPGM2 is a positive amount smaller than the amount of increase DVPGM1 (0<DVPGM2<DVPGM1)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Harada to modified Cho wherein the first time period is set to be longer as the number of program-erase cycles increases and the voltage offset is set to be smaller as the number of program-erase cycles increases in order to perform an interrupt operation without deteriorating performance of a write operation (Harada, [0115]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Grunzke (US Pub. 20160155507 A1): para. [0052] and Fig. 8 are relevant to claims 1, 15, and 17.
Lee et al. (US Pub. 20230154553 A1): paras. [0182]-[0183] and Fig. 19 are relevant to claims 1, 15, and 17.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.R.A./Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
5/16/2026
Prosecution Insights