Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shimogawa et al. (US Pub # 2010/0034040).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Shimogawa et al. teach a method, comprising: determining, at selection circuitry, whether a first word received from a first group of sense amplifiers has at least one bit having a first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043, Unit (14+15) is selection circuitry, unit 14 receive bit from sense amp group SA1..SA32); and at least while the first word is being outputted from the selection circuitry responsive to the first word being determined to have the at least one bit having the first binary value, preventing a selector configured to receive a second word from a second group of sense amplifiers from outputting the second word from the selection circuitry regardless of whether the second word has at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043, data out I/O1…I/O32 line for “1” and “0” separately and independently).
Even though Shimogawa et al. teach data bit value for first / second sense amp group but silent exclusively about first / second word. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Shimogawa et al. where unit 14 receive data with logic value “1” and data with logic value “0” i.e. data word for “1” or “0” in order to control the output for I/O lines and to have increased occurrence rate of desired data and to reduce operating current during read operation (see paragraph 0012-0013).
Regarding claim 2, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Shimogawa et al. further teach further comprising: responsive to the first word being determined to not have the at least one bit having the first binary value, allowing the selector to output the second word from the selection circuitry if the second word is determined to have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0041).
Regarding claim 3, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Shimogawa et al. further teach, further comprising: replacing the first word with a number of bits not having the first binary value responsive to the first word having been outputted from the selection circuitry; and responsive to the first word being replaced with the number of bits, allowing the selector to output the second word from the selection circuitry (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0040).
Regarding claim 4, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Shimogawa et al. further teach, further comprising: determining, at the selection circuitry, whether the second word has at least one bit having the first binary value responsive to the first word being determined to not have the at least one bit having the first binary value or being replaced with the number of bits; and responsive to the second word being determined to have the at least one bit having the first binary value, preventing a selector configured to receive a third word from a third group of sense amplifiers from outputting the third word from the selection circuitry at least while the second word is being outputted from the selection circuitry regardless of whether the third word has at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043).
Regarding claim 2, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Shimogawa et al. further teach, wherein: the selection circuitry further comprises a first circuit block to receive the first word and a second circuit block to receive the second word; and the method further comprises putting the first circuit block into a high impedance state responsive to the first word being determined to not have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0038).
Regarding claim 6, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Shimogawa et al. further teach, wherein: the selection circuitry is further coupled to a local input/output (LIO) line; and the method further comprises outputting the first word on the LIO line responsive to the first word being determined to have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0042).
Regarding independent claim 7, Shimogawa et al. teach an apparatus, comprising: a memory array; a plurality of sense amplifiers coupled to the memory array; and selection circuitry coupled to the plurality of sense amplifiers (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043, Unit (14+15) is selection circuitry, unit 14 receive bit from sense amp group SA1..SA32, MC1..MC128 are memory array), the selection circuitry comprising: a first circuit block configured to receive a first word from a first group of sense amplifiers; and a second circuit block configured to receive a second word from a second group of sense amplifiers; and the first circuit block further configured to: determine whether the first word has at least one bit having a first binary value ; and in response to the first word being determined to not have the at least one bit having the first binary value, provide a enable signal to the second circuit block to allow the second word to be outputted from the second circuit block when the second word is determined at the second circuit block to have at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043, data out I/O1…I/O32 line for “1” and “0” separately and independently with IV1 enable signal).
Even though Shimogawa et al. teach data bit value for first / second sense amp group but silent exclusively about first / second word. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Shimogawa et al. where unit 14 receive data with logic value “1” and data with logic value “0” i.e. data word for “1” or “0” in order to control the output for I/O lines and to have increased occurrence rate of desired data and to reduce operating current during read operation (see paragraph 0012-0013).
Regarding claim 8, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Shimogawa et al. further teach, further comprising: responsive to the first word being determined to not have the at least one bit having the first binary value, allowing the selector to output the second word from the selection circuitry if the second word is determined to have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0041).
Regarding claim 8, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Shimogawa et al. further teach, wherein the first circuit block of the selection circuitry further comprises a first logic gate configured to: receive the first word from the first group of sense amplifiers; and determine whether the first word has the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0040).
Regarding claim 9, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Shimogawa et al. further teach, wherein the first logic gate is a wired OR circuit (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0040).
Regarding claim 10, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Shimogawa et al. further teach, wherein the first circuit block of the selection circuitry further comprises a second logic gate coupled to the first logic gate and a selector, the second logic gate configured to: receive, from the first logic gate, an input signal indicating that the first word has the at least one bit having the first binary value; and enable the selector to allow the first word to be outputted via the selector when the first word being is determined to have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043).
Regarding claim 11, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Shimogawa et al. further teach, wherein the second logic gate is an AND gate (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0038).
Regarding claim 12, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Shimogawa et al. further teach, wherein the first circuit block of the selection circuitry further comprises a third logic gate configured to: receive, from the second logic gate, an input signal indicating that the first word is determined to have the at least one bit having the first binary value; and provide the enable signal to the second circuit block of the selection circuitry (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0041).
Regarding claim 13, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 12 on which this claim depends.
Shimogawa et al. further teach, wherein the third logic gate is an OR gate (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0039).
Regarding claim 14, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Shimogawa et al. further teach, wherein: the first and second circuit blocks of the selection circuitry are further coupled to a local input/output (LIO) line; and the first and second circuit blocks are configured to output respective words on the LIO line (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0040).
Regarding claim 15, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Shimogawa et al. further teach, wherein the memory array comprises a dynamic random access memory (DRAM) array (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0038).
Regarding claim 16, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Shimogawa et al. further teach, wherein the selection circuitry is on-chip with the memory array and the plurality of sense amplifiers (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0041).
Regarding independent claim 17, Shimogawa et al. teach an apparatus, comprising: a plurality of sense amplifiers; and selection circuitry coupled to the plurality of sense amplifiers and to one or more local input/output (LIO) lines (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043, Unit (14+15) is selection circuitry, unit 14 receive bit from sense amp group SA1..SA32); and the selection circuitry configured to determine, in response to receiving an activation signal, whether a first word received at the selection circuitry from a first group of sense amplifiers of the plurality has at least one bit having a first binary value; wherein the activation signal further causes the selection circuitry to determine whether a second word received at the selection circuitry from a second group of sense amplifiers of the plurality has at least one bit having the first binary value when the first word is determined to not have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043, data out I/O1…I/O32 line for “1” and “0” separately and independently using signal IV1).
Even though Shimogawa et al. teach data bit value for first / second sense amp group but silent exclusively about first / second word. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Shimogawa et al. where unit 14 receive data with logic value “1” and data with logic value “0” i.e. data word for “1” or “0” in order to control the output for I/O lines and to have increased occurrence rate of desired data and to reduce operating current during read operation (see paragraph 0012-0013).
Regarding claim 18, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Shimogawa et al. further teach, wherein the selection circuitry is configured to prevent, in response to the first word being determined to have the at least one bit having the first binary value, the second word from being outputted from the selection circuitry (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0040).
Regarding claim 19, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Shimogawa et al. further teach, further comprising a controller coupled to the selection circuitry and the plurality of sense amplifiers, wherein the controller is further configured to, in response to the first word being outputted on a respective one of the LIO lines: replace the first word with a number of bits not having the first binary value to cause the selection circuitry to output the second word when the second word is determined to have at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0042).
Regarding claim 20, Shimogawa et al. teach all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Shimogawa et al. further teach, wherein the selection circuitry is configured to output the second word without the first word being replaced with the number of bits when the first word is determined to not have the at least one bit having the first binary value (see Fig. 1-3, paragraph 0011-0012, 0018-0034, 0036-0043).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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