Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 3, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 14, 19
b. Pending: 1-20
Specification
The disclosure is objected to because of the following informalities:
In the Background, in the last sentence of para. [0004], make the following change:
(e.g.[[,]]: user [[be]]is able to successfully read back data stored in the non-volatile memory).
In the Detailed Description, in para. [0040], in the eighth line from the bottom of p.5, make the following change:
“as the complexity of integrated subsystems keeps growing,”
In the Detailed Description, in para. [0045], in the fifth and sixth line from the bottom of p.7, make the following change:
“the system control logic 260 (which comprises one or more electrical circuits) includes state machine 262”
In the Detailed Description, in para. [0110], at the top of p.29, make the following change:
“Figure 5C shows seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG,
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
In the sixth line of claim 1, make the following change:
“by sensing the data states using
In the ninth to tenth lines of claim 1, make the following change:
“until a first maximum number of sense operations is reached,”
In the eleventh line of claim 1, make the following change:
“count a number of non-volatile memory cells”
In the fourteenth to fifteenth lines of claim 1, make the following change:
“if the
In the sixteenth line of claim 1, make the following change:
“greater than the
In the sixteenth line of claim 1, make the following change:
“identify a first valley in the
There are similar issues with the phrase including “count of…” in claims 2, 7-10, 19 and 20.
Regarding claim 20, make the following change:
“and the means for counting a number of memory cells newly turning on at each sense operation are performed until…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2-7, 15, and 20 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claims 2, 15, and 20 depend on independent claims that teach a determination of whether one count is greater than another. Specifically, claims 1 and 19 teach that a process is ended when a current count of activated cells is greater than a previous count of activated cells, and claim 14 teaches valley identification and adjustment of a read reference level when a current bit count is greater than a previous bit count. The limitations of claims 2, 15, and 20—the determination of a percentage of difference—are not possible to meet because the “greater than” was the only comparison needed in the independent claims. Claims 3-7 depend on claim 2 and are thus rejected for the same reasons. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims complies with the statutory requirements.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 19 recites a “means for storing data in the non-volatile memory cells” and a “means for adjusting the set of read reference levels…and counting a number of memory cells newly turning on”. Claim 20, dependent on claim 19, also mentions the means for adjusting and counting. The Specification in in para. [0003] teaches “Non-volatile memory allows information to be stored”, and in para. [00149] teaches “the control circuit adjusts read reference levels”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-9, 11, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mokhlesi et al. (US Pub. 20110194348 A1; “Mokhlesi”).
Regarding independent claim 1, Mokhlesi discloses a non-volatile storage apparatus (Fig. 3: non-volatile storage device 210; [0054]), comprising:
non-volatile memory cells ([0054]: Memory die 212 includes an array (two-dimensional or three dimensional) of memory cells 200); and
a control circuit (control circuitry 220; [0054]) connected to the non-volatile memory cells ([0055]: Control circuitry 220 cooperates with the read/write circuits 230A and 230B to perform memory operations on the memory array 200. The control circuitry 220 includes a state machine 222), the control circuit is configured to store data in the non-volatile memory cells by programming the non-volatile memory cells to a set of data states ([0065]: The program operation, under the control of the state machine, comprises a series of programming voltage pulses (with increasing magnitudes) applied to the control gates of the addressed memory cells. Each programming pulse is followed by a verify process to determine if the memory cell has been programmed to the desired state), the control circuit is configured to read data stored in the non-volatile memory cells by sensing for a set of read reference levels for the data states ([0063]: During read or sensing, the operation of the system is under the control of state machine 222 that controls the supply of different control gate voltages to the addressed cell), the control circuit is further configured to:
perform a first plurality of sense operations for at least a first subset of the non-volatile memory cells at incrementally higher threshold voltages until a first maximum number of sense operations ([0090]: the behavior of the sensing circuits and the array of memory cells that are involved in measuring the conduction current of a memory cell by determining whether the bit line has discharged…If the threshold voltage in the memory cell selected for reading is below Vcgr or below the verify compare level applied to the selected word line WLn, then the memory cell selected for reading will turn on (conduct)…At some point after time t2 and prior to time t3 (as determined by the particular implementation), the sense amplifier will determine whether the bit line has dissipated a sufficient amount. At time t3, the depicted signals will be lowered to Vss (or another value for standby or recovery). Examiner concludes that a maximum number of sense operations is reached between times t2 and t3),
count number of non-volatile memory cells newly turning on at each sense operation performed of the first plurality of sense operations ([0104]: FIG. 17 is a flow chart describing one embodiment of determining threshold voltage distribution data…In step 832 a read operation is performed using the Vcgr set in step 830…The number of memory cells that conducted (turn on) in response to Vcgr being applied to their respective control gates (via the selected word line) is determined and stored (step 834)),
terminate the performing of the first plurality of sense operations prior to performing the first maximum number of sense operations if the count of number of memory cells newly turning on during a current sense operation of the first plurality of sense operations is greater than the count of number of memory cells newly turning on during a previous sense operation of the first plurality of sense operations ([0104]: The difference between the number of memory cells that conducted (turned on) in response to the current Vcgr and the number of memory cells that conducted (turned on) in response to the previous Vcgr is determined. That difference represents the number of memory cells having a threshold voltage at the current Vcgr…If there are more samples to consider (step 838), then Vcgr is incremented in step 840 and the process loops back to step 832…When the process loops back to step 832, another read operation is performed for the new Vcgr, the number of conducting memory cells is determined (step 834) and the new delta (step 836) is calculated. When there are no more samples to collect (e.g., Vcgr=5.0 volts or all memory cells have had there threshold voltage determined), then the process of FIG. 17 is complete. In another embodiment, a maximum Vcgr has been previously specified. If after step 840 the maximum Vcgr has been reached, then all remaining memory cells are assigned this maximum Vcgr. Examiner asserts that the “no more samples to collect” scenario is analogous to the count comparison limitation, and the “maximum Vcgr” scenario is analogous to “performing the first maximum number of sense operations”),
identify a first valley in the count of number of memory cells newly turning on at each sense operation performed of the first plurality of sense operations ([0105]: Distribution function (cell count as a function of control gate voltage) 860 of FIG. 18 provides one example of threshold voltage distribution data that is the result of the process of FIG. 17…FIG. 19 depicts the derivative of distribution function 862…Points 870 and 872 are two examples of zero crossings from negative values to positive values depicted in FIG. 19, and both can be read compare points. In one embodiment, the zero crossings are obtained by interpolation between pairs of neighbor derivative data. Examiner asserts that the derivative of the curve 862 at valleys is 0, so the zero crossings of Fig. 19 are valleys), and
adjust read reference levels based on the identified first valley (in reference to Fig. 16, per [0102]: In step 806, the output of derivative calculation is investigated to look for zero crossings. In one embodiment, zero crossings of the derivative data from negative derivative data values transitioning to positive derivative data values, as word line voltage is increased, represent read compare points…In step 808, the new read compare points found in step 806 are used to replace the old read compare points; [0086]: between each data state is a read compare point, such as Vra between state 0 and state 1 of FIG. 6 and Vrb between state 1 and state 2 of FIG. 6…A read process would test whether the threshold voltage of a memory cell was below each of the fifteen read compare points).
Regarding claim 8, Mokhlesi discloses the limitations of claim 1. The limitations of claim 8 are substantially the same as the limitations of claim 1 and thus are rejected for the same reasons as claim 1. Further:
perform a second plurality of sense operations for at least the first subset of the non-volatile memory cells (per Fig. 16, step 808, which is mistakenly labeled 806, old read compare points are replaced with new read compare points. This indicates that the sensing and updating process may be performed multiple times on the same group of elements determined in step 800. The following prove that there are additional sense operations for higher memory states: [0095]: the technology described herein seeks to dynamically and adaptively update the read compare points (voltage levels) based on memory cell threshold voltage distribution; claim 18: new read compare values are indications of voltage levels for differentiating between multiple data states for multi-state flash memory)
identify a second valley (it is evident from Figs. 18 that there are multiple valleys)
Regarding claim 9, Mokhlesi discloses the limitations of claim 1. Claim 9 recites substantially the same limitations as the fifth paragraph of claim 1. Further:
the count of number of memory cells newly turning on during the current sense operation of the first plurality of sense operations is greater than the count of number of memory cells newly turning on during an immediately previous sense operation of the first plurality of sense operations ([0104]: If there are more samples to consider (step 838), then Vcgr is incremented in step 840 and the process loops back to step 832. Examiner concludes that this describes adjacent sense operations).
Regarding claim 11, Mokhlesi discloses the limitations of claim 1. Further:
each of the data states correspond to threshold voltage distributions ([0010]: A multi-state memory device stores multiple bits of data per memory cell by identifying multiple distinct valid threshold voltage distributions (or data states) separated by forbidden ranges); and
each of the read reference levels are read reference voltages between peaks of the threshold voltage distributions ([0086]: between each data state is a read compare point).
Independent claim 19 is nearly identical in claimed subject matter to independent claim 1 and is rejected for the same reasons as independent claim 1.
Claims 14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tokutomi et al. (US Pub. 20220270687 A1; “Tokutomi”).
Regarding independent claim 14, Tokutomi discloses a method (Fig. 11, with emphasis on Figure 11’s step ST4 that is further detailed in Figure 12, and Figure 12’s ST20 that is further detailed in Figure 14), comprising:
(a) setting a current word line voltage as a previous word line voltage plus an increment value ([0169]: the reading voltage increases (monotonically increases) along with the progress of loop processing);
(b) applying the current word line voltage (Fig. 9: reading voltage V4; [0143]) to a word line connected to a set of non-volatile memory cells (per [0134], “target page” used for the shift reading command; Fig. 12: steps ST16 & ST17);
(c) sensing the non-volatile memory cells in response to the current word line voltage (Fig. 9: the count M4, from which M3 is subtracted; Fig. 12: steps ST17 & ST18);
(d) determining a current bit count representing a number of memory cells newly turning on in response to the current word line voltage (Fig. 9: “(M4-M3)”; also Fig. 12: step ST19-1, ST19-2, ST19-3);
(e) determining whether the current bit count (Fig. 9, “(M4-M3)”) is greater than a previous bit count (Fig. 9, “(M3-M2)”; [0140]: As shown in the middle view of FIG. 9, when the reading voltage is raised, the number of ON cells abruptly increases at a voltage slightly lower than a voltage VAmid . . . If the reading voltage is further raised, the increasing rate of the number of ON cells lowers and minimizes in a certain value. . . . If the reading voltage is further raised, the increasing rate of the number of ON cells increases again; [0141]: Based on the above-described change of the cumulative number of ON cells, the valley position between the two levels, that is, the position of the reading voltage at which the overlap between the threshold voltage distributions of the two levels is minimized can be detected);
(f) in response to determining that the current bit count is not greater than a previous bit count, repeating (a)-(f) (Fig. 12: loopback from step ST22 to ST16); and
(g) in response to determining that the current bit count (Fig. 9: “(M4-M3)”) is greater than a previous bit count (Fig. 9, “(M3-M2)”), identifying a valley (Figure 9, valley is determined between V2 & V3 because the number of ON cells increased during the (M4-M3) read operation compared to the previous (M3-M2) read operation, as explained in paragraphs [0140]-[0141]) in number of memory cells newly turning on based on the current word line voltage and adjusting read reference levels based on the identified valley (Fig. 11: step ST6 after steps ST4 & ST5).
Regarding claim 16, Tokutomi discloses the limitations of claim 14. Further:
repeating (a)-(g) for different current word line voltages ([0169]: reading voltage search direction is set such that the reading voltage increases (monotonically increases) along with the progress of loop processing), the adjusting read reference levels is also based on the identified valley from repeating (a)-(g) for different current word line voltages (Fig. 12: ST20-1, ST20-2, ST20-3; per Fig. 12, shift amounts are determined based on the detection of valley positions).
Regarding claim 17, Tokutomi discloses the limitations of claim 14. Further:
the previous bit count is an immediately previous bit count (Fig. 14: ST42; [0202]: In step ST42, the controller 200 determines whether the bit count ΔBm is not less than the bit count ΔB(m−1)); and
the applying the current word line voltage to the word line connected to the set of non-volatile memory cells causes memory cells of the set of non-volatile memory cells to turn on if the respective memory cells have threshold voltages less than or equal to the current word line voltage ([0120]: when the voltage Vt is applied to the selected word line WL to turn on the memory cell transistor MT, a current flows from the bit line BL to the source line SL. As a result, the node SEN is discharged, and the potential of the node SEN lowers. The sense amplifier SA asserts the signal STB at the time T2, thereby fetching the state of the node SEN to the internal latch circuit. That is, if the potential of the node SEN is low, one of data “0” and data “1” is stored in the latch circuit).
Regarding claim 18, Tokutomi discloses the limitations of claim 14. Further:
reading data from the set of non-volatile memory cells using the adjusted read reference levels (Fig. 12: ST16, ST17, ST18, ST23 show reading with shifted reading voltages).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7, 10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi (US Pub. 20110194348 A1) as applied to claims 1 and 19 above, respectively, and further in view of Kumar et al. (US Pub. 20160133333 A1; “Kumar”).
Regarding claim 2, Mokhlesi discloses the limitations of claim 1. Mokhlesi does not disclose:
the control circuit is configured to terminate the performing of the first plurality of sense operations prior to performing the first maximum number of sense operations if the count of number of memory cells newly turning on during the current sense operation is greater by a predetermined percentage than the count of number of memory cells newly turning on during a previous sense operation.
However, Kumar teaches:
the control circuit ([0045]: The storage controller 401 may include a storage interface 404. The storage interface 404 receives the placed thresholds from the placed threshold generator 402 and performs reads on the solid state storage 450 using the placed thresholds) is configured to terminate the performing of the first plurality of sense operations prior to performing the first maximum number of sense operations if the count of number of memory cells newly turning on during the current sense operation is greater by a predetermined percentage than the count of number of memory cells newly turning on during a previous sense operation ([0056]: As shown in FIG. 7, the procedure for finding the minimum bin may stop at the nth read if (B.sub.n−A.sup.(n).sub.min)>T2 where B.sub.n=1.sub.CD(R.sub.n-1,R.sub.n). The value of T2 is chosen heuristically depending upon the NAND data).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kumar to Mokhlesi wherein the control circuit is configured to terminate the performing of the first plurality of sense operations prior to performing the first maximum number of sense operations if the count of number of memory cells newly turning on during the current sense operation is greater by a predetermined percentage than the count of number of memory cells newly turning on during a previous sense operation in order to improve data integrity by estimating the optimal read threshold (Kumar, [0030]).
Regarding claim 3, Mokhlesi and Kumar together discloses the limitations of claim 2, and further through Kumar:
the control circuit is configured to set the predetermined percentage ([0056]: The value of T2 is chosen heuristically depending upon the NAND data; [0046]: The storage controller 401 may include a bit flip calculator 406 and an optimal threshold estimator 408. The storage interface 404 may pass the read-back bit sequences to bit flip calculator 406…The optimal threshold estimator 408 in turn generates an estimated threshold, including by determining a minimum (e.g., a minimum bit, a minimum bin, etc.)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kumar to modified Mokhlesi wherein the control circuit is configured to set the predetermined percentage in order to improve data integrity by estimating the optimal read threshold (Kumar, [0030]).
Regarding claim 4, Mokhlesi and Kumar together discloses the limitations of claim 2, and further through Kumar:
the control circuit is configured to adjust the predetermined percentage ([0042]: The storage controller 401 may perform optimal threshold estimation).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kumar to modified Mokhlesi wherein the control circuit is configured to adjust the predetermined percentage in order to improve data integrity by estimating the optimal read threshold (Kumar, [0030]).
Regarding claim 5, Mokhlesi and Kumar together discloses the limitations of claim 2, and further through Mokhlesi:
the control circuit includes a register for storing the predetermined percentage ([0102]: the new read compare points are stored as parameters in registers/latches in the controller 244 or control circuitry 220 to be used immediately. Examiner asserts that it is known to a person with ordinary skill in the art to use registers to store operating parameters).
Regarding claim 6, Mokhlesi and Kumar together discloses the limitations of claim 2, and further through Mokhlesi:
a second subset of the non-volatile memory cells are configured to store the predetermined percentage ([0102]: In another embodiment, the new read compare points are stored as parameters in non-volatile memory for future use).
Regarding claim 7, Mokhlesi and Kumar together discloses the limitations of claim 2. Claim 7 recites exactly the same limitations as claim 8 except claim 7 further specifies that the determination of a greater memory cell count is “by a predetermined percentage”, which is a claim 2 limitation rejected above. Thus, claim 7 is rejected for the same reasons as claims 2 and 8.
Regarding claim 10, Mokhlesi discloses the limitations of claim 1. Claim 10 recites substantially the same limitations as claims 2 and 9, and henceforth is rejected for the same reasons.
Regarding claim 20, Mokhlesi discloses the limitations of claim 19. Claim 20 recites substantially the same limitations as claims 2 and 19, and henceforth is rejected for the same reasons.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi (US Pub. 20110194348 A1) as applied to claim 1, and further in view of Tokutomi (US Pub. 20220270687 A1).
Regarding claim 12, Mokhlesi discloses the limitations of claim 1. Further through Mokhlesi:
a first word line connected to the control circuit ([0055]: The power control module 226 controls the power and voltages supplied to the word lines and bit lines during memory operations; also see Fig. 3) and the first subset of non-volatile memory cells ([0058]: memory cells along a common word line; also see Fig. 4), the control circuit is configured to perform the first plurality of sense operations ([0063]) by:
Mokhlesi does not disclose:
setting a current word line voltage as a previous word line voltage plus an increment value,
applying the current word line voltage to the first word line, and
sensing the first subset of non-volatile memory cells in response to the current word line voltage.
However, these limitations of claim 12 are substantially the same as method steps (a)-(c) of claim 14, and thus are rejected for the same reasons.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tokutomi to modified Mokhlesi wherein the control circuit performs sense operations by setting a current word line voltage as a previous word line voltage plus an increment value, applying the current word line voltage to the first word line, and sensing the first subset of non-volatile memory cells in response to the current word line voltage in order to speed up reading operations and improve reading performance by tracking threshold voltages (Tokutomi, [0259]).
Regarding claim 13, Mokhlesi and Tokutomi together disclose the limitations of claim 12. Further through Tokutomi:
the non-volatile memory cells are arranged as vertical NAND strings ([0071]: As shown in FIG. 2, the block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings 6) in a three dimensional memory structure ([0082]: The memory cell array 110 may have another configuration. That is, an configuration of the memory cell array 110 is described in, for example, U.S. patent application Ser. No. 12/407,403 “THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY” filed on Mar. 19, 2009); and
each of the memory cells of the first subset of non-volatile memory cells are positioned on different NAND strings ([0140]: V is the reading voltage applied to the selected word line WL).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tokutomi to modified Mokhlesi wherein the non-volatile memory cells are arranged as vertical NAND strings in a three dimensional memory structure, and each of the memory cells of the first subset of non-volatile memory cells are positioned on different NAND strings in order to speed up reading operations and improve reading performance by tracking threshold voltages (Tokutomi, [0259]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tokutomi (US Pub. 20220270687 A1) as applied to claim 14 above, and further in view of Kumar (US Pub. 20160133333 A1).
Regarding claim 15, Tokutomi discloses the limitations of claim 14. Claim 15 recites substantially the same limitations as step (e) of claim 14 combined with limitations of claims 2 and 20, and henceforth is rejected for the same reasons.
Conclusion
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
/E.R.A./Examiner, Art Unit 2824
5/15/2026
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