Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, ‘Figures 3A-3L’ in the paragraph [0009], ‘Figures 5A-5L’ in the paragraph [0011], ‘Figures 7A-7D’ in the paragraph [0013] and ‘Figures 9A-9H’ in the paragraph [0015] are objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 26-27, 29, 30, 32, 37 and 39 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 26, the limitation "the surface of the metallization layer" lacks proper antecedent basis because no surface of the metallization layer has been previously introduced in the claim.
Suggested correction
Introduce the surface when the metallization layer is first recited. For example:
"...providing an element having a metallization layer having a surface, the metallization layer comprising a field dielectric and a conductive feature embedded in the field dielectric..."
Then later:
"...forming a dielectric layer over the surface of the metallization layer..."
Regarding claims 27, 29, 30, 32, 37 and 39, because of their dependency on claim 26, these claims are also rejected for the reasons set forth above with respect to claim 26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 20150357296).
Regarding claim 1. Liu discloses a method of forming a microelectronic component, the method comprising:
providing an element having a metallization layer comprising a field dielectric (insulating material 114U) and a conductive feature (110) embedded in the field dielectric ([0025]; FIG. 6E);
forming a copper feature (conductive pad 112) over the conductive feature, wherein the conductive pad comprises copper or a copper alloy ([0026]; FIG. 6E);
after forming the copper feature, forming a dielectric layer (160) over sidewalls of the copper feature, as shown in FIG. 6F; and
planarizing the dielectric layer (160) to form a hybrid bonding surface, wherein the copper feature 112 is exposed at the hybrid bonding surface, as shown in FIG. 6G.
Regarding claim 17. Liu discloses the method of claim 1, wherein the element comprises a first element having a first hybrid bonding surface. Liu further teaches providing a second element having a second hybrid bonding surface, as shown in FIG. 8A, where the upper semiconductor element is positioned above the first semiconductor element in preparation for hybrid bonding. Liu further teaches hybrid bonding the first hybrid bonding surface of the first element to the second hybrid bonding surface of the second element, as shown in FIGS. 8B and 8C, thereby forming a hybrid-bonded semiconductor structure.
Regarding claim 19. Liu discloses the method of Claim 1, wherein the dielectric layer (160) comprises silicon Nitride. Specifically, Liu teaches that dielectric layer 160 is formed of SiN [0034]. Therefore, Liu discloses the claimed dielectric layer composition.
Regarding claim 20. Liu discloses the method of Claim 1, wherein the dielectric layer comprises a first dielectric layer (160B). After formation of the first dielectric layer 160B over the sidewalls of the copper feature 112² (FIG. 6E), Liu further forms a second dielectric layer (114T) over the first dielectric layer, as shown in FIG. 6F, wherein the first dielectric layer 160B is disposed directly beneath the second dielectric layer 114T. FIGS. 6E–6G illustrate the sequential process flow for forming the hybrid bonding structure.
Claims 26-27 and 37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated Kwon et al. (US 20230114550).
Regarding claim 26. Kwon discloses a method of forming a bonded structure comprising:
providing a first element having a metallization layer that comprises a dielectric layer 151 [0027] and a plurality of conductive features 130 embedded in the dielectric layer ([0024]; Fig. 3);
forming a bonding layer over the metallization layer (Fig. 3), wherein the bonding layer comprises a dielectric material 171 [0032] and a plurality of copper features 175 ( [0031]; Fig. 1);
wherein at least one of the plurality of copper features 175 is electrically connected to one of the plurality of conductive features 130 (Figs. 1 and 3);
wherein the exposed surfaces of the dielectric material 171 and the plurality of copper features 175 define a first hybrid bonding surface of the bonding layer [0037]; Fig. 3);
wherein the dielectric material 171 comprises an oxide material, specifically silicon oxide (SiO₂) [0032], that directly contacts the sidewalls of each of the plurality of copper features 175 (Fig. 3);
preparing the first hybrid bonding surface for hybrid bonding (Fig. 3, Fig. 4, element 100A);
providing a second element having a second hybrid bonding surface (Fig. 4, element 100B′); and
hybrid bonding the first hybrid bonding surface to the second hybrid bonding surface to form the bonded structure (Fig. 4).
Regarding claim 27. Kwon discloses the method of claim 26, wherein forming the bonding layer over the metallization layer comprises:
forming the plurality of copper features 175 over the plurality of conductive features 130 (Figs. 7D and 7E); and
after forming the plurality of copper features 175, depositing the dielectric material 171 over the metallization layer and into gaps between adjacent ones of the plurality of copper features such that the sidewalls of each of the plurality of copper features are covered by the dielectric material (Fig. 7F; [0031]-[0032]).
As shown in FIG. 7F, the deposited dielectric material 171 fills the spaces between adjacent copper features 175 and directly contacts and covers the sidewalls of each copper feature, thereby forming the bonding layer recited in the claim.
Regarding claim 37. Kwon discloses the method of claim 26, wherein the oxide material comprises silicon oxide. Specifically, Kwon teaches that the dielectric material 171 may comprise silicon oxide (SiO₂) [0032]. As discussed with respect to claim 26, dielectric material 171 forms part of the bonding layer and directly contacts the sidewalls of the copper features 175 (Fig. 3; [0032]).
Claims 40-41 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang (US 20240063152).
Regarding claim 40. Wang discloses a microelectronic component (FIG. 3D) comprising:
an element having a metallization layer including a first dielectric layer (304) and a conductive feature (bond pad 302) embedded in the first dielectric layer (FIG. 3D);
a bonding layer formed over the metallization layer, wherein the bonding layer comprises:
a second dielectric layer (312); and
a copper feature (bond pad 310), wherein the copper feature is electrically connected to the conductive feature (bond pad 302) through hybrid bonding (FIG. 3D).
Further, the second dielectric layer 312 directly contacts the sidewalls of the copper feature 310, as shown in FIG. 3D, where no intervening layer is present between dielectric layer 312 and the sidewalls of copper feature 310.
Further, the second dielectric layer 312 and the copper feature 310 form a hybrid bonding surface of the bonding layer, as Wang teaches that, after completing the hybrid bonding process, a second thermal anneal forms metal-to-metal bonds between bond pads 302 and 310, while the conductive material expands toward each other at the bonding interface due to the coefficient of thermal expansion mismatch with the dielectric materials, thereby completing the hybrid bonding structure [0039].
Regarding claim 41. Wang discloses the microelectronic component of Claim 40, wherein the bonding layer further comprises a barrier layer disposed between the copper feature 310 and the conductive feature 302.
Specifically, FIG. 3C illustrates layer 308 disposed between bond pad 302 and bond pad 310. Chen teaches that layer 308 is selectively formed on the bond pad 302 and comprises a metal nitride composite, such as copper nitride (Cu₃N) generated by a plasma deposition process ([0029]-[0032]). Chen further teaches that layer 308 isolates the conductive bond pad material from oxygen and reduces formation of metal oxide during the hybrid bonding process, thereby functioning as a barrier layer [0033]. Accordingly, Chen discloses the claimed barrier layer disposed between the conductive feature and the copper feature.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20150357296) in view of Kwon et al (US 20230114550).
Regarding claim 2. Liu discloses the method of claim 1. But Liu does not expressly disclose that the dielectric layer comprises silicon oxide and that forming the dielectric layer over the sidewalls of the copper feature comprises forming the dielectric layer such that the silicon oxide directly contacts the sidewalls of the copper feature.
However, Kwon teaches a semiconductor device including upper bonding pad 175, which is a copper feature ([0031]: "The lower bonding pad 145 and the upper bonding pad 175 may include the same metal, for example, copper (Cu)."). Kwon further teaches upper insulating layer 171 surrounding the upper bonding pad 175. As shown in Fig. 3, the upper insulating layer 171 directly contacts the sidewalls of the upper bonding pad 175. Additionally, Kwon teaches that the upper insulating layer 171 may comprise silicon oxide (SiO₂) ([0032]: "the upper insulating layer 171 and the lower insulating layer 141 may include at least one of silicon oxide (SiO₂)...").
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liu to form the dielectric layer from the silicon oxide material taught by Kwon such that the silicon oxide directly contacts the sidewalls of the copper feature, because doing so provides electrical insulation and facilitates dielectric bonding in hybrid bonding structures.
Regarding claim 14. Liu discloses the method of claim 1. But Liu does not expressly disclose a process for forming the copper feature over the conductive feature comprising a seed layer, patterned plating, and subsequent seed layer removal.
However, Kwon teaches forming the copper feature over the conductive feature by:
forming a seed layer 164 over the metallization layer (Fig. 7B; [0056]), wherein the seed layer comprises a first portion over the conductive feature 130 and a second portion over the field dielectric 151;
forming and patterning a mask (photoresist pattern PR) over the seed layer to form an opening positioned over the conductive feature, wherein the first portion of the seed layer is exposed through the opening (Fig. 7C; [0058]);
plating copper metal into the opening and over the first portion of the seed layer to form the copper feature 175 (Fig. 7C; [0058]-[0059]);
removing the mask to expose the second portion of the seed layer (Fig. 7D; [0060]); and
removing the second portion of the seed layer by etching the exposed portion of the seed layer (Fig. 7D; [0061]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Kwon's seed-layer plating process in the method of Liu because both references are directed to fabricating copper interconnect structures for hybrid bonding semiconductor devices. Kwon's process provides a well-known and reliable technique for forming copper features on underlying conductive features while removing excess seed material to electrically isolate adjacent copper features, thereby yielding predictable results.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20150357296) in view of Jang et al. (US 20160141282).
Regarding claim 21. Liu discloses the method of Claim 20. But Liu does not expressly disclose that the first dielectric layer comprises silicon oxide and the second dielectric layer comprises silicon nitride.
However, Jang discloses these material compositions. Specifically, FIG. 3 and paragraph [0044] disclose that the first insulating interlayer 130, corresponding to the claimed first dielectric layer, may be formed of an oxide, e.g., silicon oxide. Further, FIG. 4 and paragraph [0051] disclose that the first bonding insulating layer structure 180, corresponding to the claimed second dielectric layer, may include a nitride, e.g., silicon nitride.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu by forming the first dielectric layer of silicon oxide and the second dielectric layer of silicon nitride as taught by Jang, because Jang teaches that these dielectric materials are suitable insulating layers for hybrid bonding structures and provide the desired insulating and bonding characteristics.
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (US 20230114550).
Regarding claim 39. Kwon discloses the method of claim 26, including forming a bonding layer comprising dielectric material 171 and a plurality of copper features 175, wherein the dielectric material directly contacts the sidewalls of the copper features (Fig. 3; Fig. 7D; [0032], [0058]-[0061]).
But Kwon does not expressly disclose that the sidewalls of each of the plurality of copper features comprise copper oxide.
However, Kwon teaches forming the copper features 175 (Fig. 7C; [0058]-[0059]), followed by removal of the photoresist pattern and etching of the exposed portions of the seed layer to expose the sidewalls of the copper features (Fig. 7D; [0060]-[0061]).
Thus, it would have been obvious to one of ordinary skill in the art that the exposed copper sidewalls would form a native copper oxide layer upon exposure to an oxygen-containing environment before or during the subsequent deposition of dielectric material 171, as the formation of a native copper oxide layer on exposed copper surfaces is a well-known and predictable phenomenon. The subsequently deposited dielectric material 171 would therefore directly contact the native copper oxide layer.
Accordingly, it would have been obvious to modify Kwon such that the sidewalls of each of the plurality of copper features comprise copper oxide and the dielectric material directly contacts the copper oxide, as recited in claim 39.
Claims 50 and 55 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20240063152) in view of Kwon et al (US 20230114550).
Regarding claim 50. Wang discloses the microelectronic component of claim 40. But Wang does not expressly disclose that the element comprises a first element having a first hybrid bonding surface, a second element having a second hybrid bonding surface, and that the first hybrid bonding surface is hybrid bonded to the second hybrid bonding surface such that the dielectric layers are directly bonded without an intervening adhesive and the copper features are directly bonded by a metal-to-metal bond.
However, Kwon teaches a first element (first semiconductor chip 100A) having a first hybrid bonding surface (BS1) and a second element (second semiconductor chip 100B) having a second hybrid bonding surface (BS2) (Fig. 4; [0029]). The second hybrid bonding surface comprises a second conductive feature 145 ([0024]) and a fourth dielectric layer 141 [0028]. Kwon further teaches hybrid bonding the first hybrid bonding surface to the second hybrid bonding surface such that the second dielectric layer 171 of the first element is directly bonded to the fourth dielectric layer 141 of the second element without an intervening adhesive, and the copper feature 175 of the first element is directly bonded to the second conductive feature 145 of the second element by a metal-to-metal direct bond (Fig. 4; [0029]-[0030]). Specifically, paragraph [0030] teaches that the upper bonding pad 175 of the first semiconductor chip 100A and the lower bonding pad 145 of the second semiconductor chip 100B are directly bonded to each other to provide an electrical connection between the semiconductor chips, while the opposing dielectric layers are directly bonded to one another.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Kwon's hybrid bonding structure into the bonded structure of Wang because both references are directed to hybrid bonding of semiconductor elements using dielectric-to-dielectric direct bonding and copper-to-copper direct bonding to provide robust mechanical attachment and reliable electrical interconnection. The combination would have yielded predictable results.
Regarding claim 55. Wang discloses the microelectronic component of claim 40. But Wang does not expressly disclose that the sidewalls of the copper feature comprise copper oxide, wherein the second dielectric layer directly contacts the copper oxide.
However, Kwon teaches forming a copper feature 175 on a seed layer 164 (Fig. 7C; [0058]-[0059]). Kwon further teaches removing the photoresist pattern and etching the exposed portions of the seed layer to expose the sidewalls of the copper feature (Fig. 7D; [0060]-[0061]). Thus, the sidewalls of the copper feature are exposed prior to formation of the dielectric material 171.
Although Kwon does not expressly disclose that the exposed sidewalls comprise copper oxide, it would have been obvious to one of ordinary skill in the art that the exposed copper sidewalls would form a native copper oxide layer upon exposure to an oxygen-containing environment before or during the subsequent deposition of dielectric material 171, since the formation of a native copper oxide layer on exposed copper surfaces is a well-known and predictable phenomenon.
Thus. it would have been further obvious to incorporate this well-known characteristic into the bonded structure of Wang because the subsequently formed second dielectric layer would directly contact the native copper oxide layer on the copper feature, thereby meeting the claimed limitation. The combination merely applies the known and inevitable surface oxidation of exposed copper during fabrication to the hybrid bonding structure of Wang and would have yielded predictable results.
Allowable Subject Matter
Claims 4-5, 11 and 44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the dielectric layer comprises a first dielectric layer, the method further comprising: before forming the copper feature over the conductive feature, forming a second dielectric layer over the metallization layer; and forming a via in the second dielectric layer to expose a portion of the conductive feature through the second dielectric layer, wherein, after forming the copper feature over the conductive feature, at least a portion of the copper feature is within the via”.
Regarding claim 44. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a third dielectric layer formed between the second dielectric layer and the first dielectric layer wherein the third dielectric layer comprises a via and wherein the copper feature electrically connects to the conductive feature through the via”.
Claims 29-30 and 32 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 29. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the dielectric material comprises a first dielectric material and wherein forming the bonding layer over the surface of the metallization layer comprises: before forming the plurality of copper features, depositing a second dielectric material over the surface of the metallization layer; and forming a plurality of vias in the second dielectric material, wherein each of the plurality of vias is formed over one of the plurality of conductive features, and wherein forming the plurality of copper features over the plurality of conductive features comprises filling each of the plurality of vias with copper metal”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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