DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US PGPub 20220130799 A1; hereinafter referred to as "Jang”) in view of Lii et al. (US PGPub 20220238353 A1; hereinafter referred to as "Lii”) and further in view of Kannojia et al. (“A review of intermetallic compound growth and void formation in electrodeposited Cu–Sn Layers for microsystems packaging,” pg. 6742-6777; hereinafter referred to as “Kannojia”).
Re claim 1: Jang teaches a semiconductor package (FIG. 1; para. 9) comprising: a first semiconductor chip (FIG. 1: el. 100; para. 22-25); a chip structure on the first semiconductor chip (FIG. 1: el. 200, 300, 400; para. 22-25; chip structure formed of semiconductor chips stacked on top of semiconductor chip 100); and a bonding structure between the first semiconductor chip and the chip structure (annotated FIG. 2: el. PAD1-1, PAD3-2; para. 36), wherein the bonding structure comprises: a first conductive pad (annotated FIG. 2: el. PAD1-1; para. 36 | first conductive pad PAD1-1 labelled in annotated FIG. 2 provided below) on an upper surface of the first semiconductor chip (annotated FIG. 2: el. 100, PAD1-1; para. 32, 35-36); a second conductive pad (annotated FIG. 2: el. PAD3-2; para. 36 | second conductive pad PAD3-2 labelled in annotated FIG. 2 provided below) on a lower surface of the chip structure (annotated FIG. 2: el. 200, PAD3-2; para. 36); wherein the upper surface of the first semiconductor chip and the lower surface of the chip structure directly contact each other (FIG. 1, 2: el. 100, 200; para. 47 | upper surface of first semiconductor chip 100 in contact with lower surface of bottom semiconductor chip 200 of the chip structure), wherein the semiconductor package further comprises a first interface between the first semiconductor chip and the chip structure (FIG. 1, 2: el. 100, 200 | first interface formed of interface between semiconductor chip 100 and semiconductor chip 200). Jang fails to teach a protective metal layer between the first conductive pad and the second conductive pad; and an intermetallic compound in the protective metal layer, wherein the protective metal layer covers a surface of the first conductive pad and a surface of the second conductive pad, wherein the semiconductor package further comprises a second interface between the protective metal layer and the second conductive pad, and wherein a first level of the first interface is equal to or lower than a second level of the second interface.
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In a similar field of endeavor, Lii teaches bonding stacked dies or wafers using direct metal-to-metal bonding of metal bond pads (FIG. 6, 18A, 18B; para. 25, 40, 56), and teaches a protective metal layer (FIG. 18A, 18B: el. 59; para. 41-43) between a first bond pad of an upper surface of a lower die and a second bond pad of a lower surface of an upper die (FIG. 6, 18A: el. 54, 154; para. 39-40). Lii teaches a semiconductor package (abstract) comprising: a bonding structure, wherein the bonding structure comprises: a first conductive pad (FIG. 18A: el. 54; para. 40) on an upper surface of the first semiconductor chip (FIG. 6-7: el. 4; para. 13); a second conductive pad (FIG. 6-7: el. 4; para. 13) on a lower surface of the chip structure (FIG. 6-7: el. 112; para. 36-37); a protective metal layer (FIG. 18A: el. 59; para. 41-43 | protective metal layer 59 formed from inter-diffusion region of fill-in metal layers 58 and 158) between the first conductive pad (FIG. 18A: el. 54; para. 40) and the second conductive pad (FIG. 18A: el. 154; para. 40); wherein the protective metal layer covers a surface of the first conductive pad and a surface of the second conductive pad (FIG. 18A: el. 59, 54’, 154’; para. 35, 38, 41-43, 46), wherein the upper surface of the first semiconductor chip (FIG. 6-7, 18A: el. 42; para. 13, 22 | dielectric layer 42 forms upper surface of first semiconductor chip 4) and the lower surface of the chip structure directly contact each other (FIG. 6-7, 18A: el. 142; para. 36-37 | dielectric layer 142 forms lower surface of semiconductor chip structure 112 and directly contacts dielectric layer 42 which forms the upper surface of first semiconductor chip 4), wherein the semiconductor package further comprises a first interface between the first semiconductor chip and the chip structure (FIG. 18A | first interface formed of interface between dielectric layer 42 of first semiconductor chip and dielectric layer 142 of semiconductor chip structure) and a second interface between the protective metal layer and the second conductive pad (FIG. 18A | second interface formed of interface between protective metal layer 59 and second conductive pad 154’ (para. 38: sent. 4)), and wherein a first level of the first interface is equal to or lower than a second level of the second interface (FIG. 18A | first level of first interface is lower than a second level of the second interface as shown in annotated FIG. 18A provided below). Lii also teaches a benefit of the protective metal layer is a reduction of non-coplanar dishing problems and a reduction in the pressure applied to achieve bonding (para. 3, 27, 39).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jang and Lii, to enable using the bonding structure of Lii in the semiconductor package of Jang, for the benefit of reducing bond pad dishing problems and reducing the applied bonding pressure.
The combination of Jang and Lii fails to directly disclose an intermetallic compound in the protective metal layer.
In a similar field of endeavor, Kannojia teaches forming a metal-to-metal bond between substrates by forming an intermetallic Cu-Sn compound in a protective metal layer at the interface between bond pads (pg. 6744: para. 1; pg. 6746: FIG. 2). Kannojia teaches an intermetallic compound in the protective metal layer (pg. 6744: para. 1; pg. 6746: FIG. 2). Kannojia also teaches that forming a Cu-Sn intermetallic compound in the protective metal layer results in the combined benefits of a low bonding pressure, a low bonding temperature, and the formation of a bonding material which is stable at temperatures higher than the bonding temperature, as well as a lower cost compared to an interfacial protective metal layer comprising indium and copper. (pg. 6744: para. 1; pg. 6746: para. 2).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kannojia and the teachings of the combination of Lii and Jang, to enable using the intermetallic compound of Kannojia in the protective metal layer of the bonding structure of the combination of Lii and Jang, for the combined benefits of low bonding pressures, low bonding temperatures, and low cost.
Re claim 2: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 1, wherein the chip structure comprises a second semiconductor chip (Jang - FIG. 1: el. 200; para. 25-26), a third semiconductor chip (Jang - FIG. 1: el. 300; para. 25-26), a fourth semiconductor chip (Jang - FIG. 1: el. 400; para. 25-26), and a fifth semiconductor chip (Jang - para. 25-26 | Jang teaches a fifth semiconductor chip in the semiconductor chip stack as Jang teaches that the plurality of semiconductor chips may be the same semiconductor chip and the plurality of semiconductor chips is not limited to four semiconductor chips) that are sequentially stacked (Jang - FIG. 1).
Re claim 3: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 2, wherein the first semiconductor chip further comprises a first through via (Jang - FIG. 1: el. 120; para. 28), wherein the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, and the fifth semiconductor chip each comprise a second through via (Jang - FIG. 1: el. 220; para. 28), wherein the first through via is connected to the first conductive pad (Jang - FIG. 1: el. 120, PAD1; para. 36), and wherein each of the second through vias are connected to the second conductive pad (Jang – annotated FIG. 1: el. 220, PAD3-2 | second through vias are labelled in annotated FIG. 1 provided below, which shows connection of second through vias to the second conductive pad).
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Re claim 4: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 1, wherein the first semiconductor chip further comprises a first upper passivation layer (Jang - FIG. 1: el. 185; para. 32) on the upper surface of the first semiconductor chip (Jang - FIG. 1: el. 100, 185) and a first lower passivation layer (Jang - FIG. 1: el. 102; para. 23) on a lower surface of the first semiconductor chip (Jang - FIG. 1: el. 100, 102), wherein the chip structure further comprises a second lower passivation layer (Jang - FIG. 1: el. 215; para. 33) on the lower surface of the chip structure (Jang - FIG. 1: el. 200, 215), and wherein the first upper passivation layer directly contacts the second lower passivation layer (Jang - FIG. 1: el. 185, 215).
Re claim 5: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 1, wherein the bonding structure further comprises a diffusion barrier layer (Lii – FIG. 18A: el. 48, 148; para. 24, 38) surrounding the first conductive pad (Lii – FIG. 18A: el. 54) and the second conductive pad (Lii – FIG. 18A: el. 154).
Re claim 6: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 1, further comprising a third interface between the protective metal layer and the first conductive pad (Lii - FIG. 18A | third interface formed of interface between protective metal layer 59 and first conductive pad 54’ (para. 35)), wherein the second interface and the third interface have a concavo-convex structure (Lii – para. 28 | Lii teaches that the micro recesses of FIG. 15B can happen at the same time as dishing, which results from chemical mechanical polishing, and that the micro recesses of FIG. 15B can happen on the dished structure of FIG. 15A; micro recesses are a well-known artifact of a chemical mechanical polishing process; the result of the micro recesses of FIG. 15B on the dished structure of FIG. 15A is the formation of undulations on the surface of the protective metal layer 59 of FIG. 18A, in similar form to the undulations formed in the protective metal layer 59 of FIG. 18B; the resulting structure of the protective metal layer 59 has a concavo-convex structure at the interface with second conductive pad 154’ (corresponding to the second interface) and first conductive pad 54’(corresponding to the third interface)). As an illustrative evidentiary example, Kung shows a concavo-convex structure at an interface between a protective metal layer and adjacent chemically mechanically polished copper conductive pads (“Investigation of Low-Pressure Sn-Passivated Cu-to-Cu Direct Bonding in 3D-Integration,” FIG. 8, pg. 6-7, Kung et al).
Re claim 7: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 1, wherein a thickness of a center of the protective metal layer is greater than a thickness of an edge of the protective metal layer (Lii – FIG. 18A: el. 59).
Re claim 9: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 1, wherein the protective metal layer comprises at least one of gold, silver, nickel, and tin (Kannojia - pg. 6744: para. 1; pg. 6746: para. 2 | Kannojia teaches a Cu-Sn intermetallic compound in the protective metal layer), and wherein the intermetallic compound comprises copper and at least one of gold, silver, nickel, and tin (Kannojia - pg. 6744: para. 1; pg. 6746: para. 2 | Kannojia teaches a Cu-Sn intermetallic compound in the protective metal layer).
Re claim 10: Jang teaches a semiconductor package (FIG. 1; para. 9) comprising: a first semiconductor chip (FIG. 1: el. 100; para. 22-25) comprising: a first upper conductive pad (annotated FIG. 2: el. PAD1-1; para. 36 | first upper conductive pad PAD1-1 labelled in annotated FIG. 2, provided in Re claim 1 section) on an upper surface of the first semiconductor chip (annotated FIG. 2: el. 100, PAD1-1; para. 32, 35-36); a first lower conductive pad (FIG. 1: el. 105; para. 62) on a lower surface of the first semiconductor chip (FIG. 1: el. 100, 105; para. 62); and a first through via (FIG. 1: el. 120; para. 49) connected to the first upper conductive pad and the first lower conductive pad (annotated FIG. 1: el. 120, PAD1-1, 105); a second semiconductor chip (FIG. 1: el. 200; para. 25-26), a third semiconductor chip (FIG. 1: el. 300; para. 25-26), a fourth semiconductor chip (FIG. 1: el. 400; para. 25-26), and a fifth semiconductor chip (para. 25-26 | Jang teaches a fifth semiconductor chip in the semiconductor chip stack as Jang teaches that the plurality of semiconductor chips may be the same semiconductor chip and the plurality of semiconductor chips is not limited to four semiconductor chips) sequentially stacked on the first semiconductor chip (FIG. 1), wherein the second semiconductor chip comprises: a second upper conductive pad (annotated FIG. 2: el. PAD1-2; para. 32, 35-36 | second upper conductive pad labelled in annotated FIG. 2, provided in Re claim 1 section) on an upper surface of the second semiconductor chip (annotated FIG. 2: el. 200, PAD1-2); and a second lower conductive pad (annotated FIG. 2: el. PAD3-2; para. 36 | second lower conductive pad PAD3-2 labelled in annotated FIG. 2, provided in Re claim 1 section) on a lower surface of the second semiconductor chip (annotated FIG. 2: el. 200, PAD3-2; para. 36); and a first bonding structure between the first semiconductor chip and the second semiconductor chip, wherein the first bonding structure comprises: the first upper conductive pad; the second lower conductive pad (annotated FIG. 2: el. PAD1-1, PAD3-2), wherein the upper surface of the first semiconductor chip and the lower surface of the second semiconductor chip directly contact each other (FIG. 1, 2: el. 100, 200; para. 47 | upper surface of first semiconductor chip 100 in contact with lower surface of bottom semiconductor chip 200 of the chip structure), wherein the semiconductor package further comprises a first interface between the first semiconductor chip and the second semiconductor chip (FIG. 1, 2: el. 100, 200 | first interface formed of interface between semiconductor chip 100 and semiconductor chip 200). Jang fails to teach a protective metal layer between the first upper conductive pad and the second lower conductive pad; an intermetallic compound in the protective metal layer; and a diffusion barrier surrounding the first upper conductive pad and the second lower conductive pad, wherein the protective metal layer covers a surface of the first upper conductive pad and a surface of the second lower conductive pad; and a second interface between the protective metal layer and the second lower conductive pad, and wherein a first level of the first interface is equal to or lower than a second level of the second interface.
In a similar field of endeavor, Lii teaches bonding stacked dies or wafers using direct metal-to-metal bonding of metal bond pads (FIG. 6, 18A, 18B; para. 25, 40, 56), and teaches a protective metal layer (FIG. 18A, 18B: el. 59; para. 41-43) between a first bond pad of an upper surface of a lower die and a second bond pad of a lower surface of an upper die (FIG. 6, 18A: el. 54, 154; para. 39-40). Lii teaches a semiconductor package (abstract) comprising: a first upper conductive pad (FIG. 18A: el. 54; para. 40) on an upper surface of the first semiconductor chip (FIG. 6-7: el. 4; para. 13); a second lower conductive pad (FIG. 18A: el. 154; para. 40) on a lower surface of the second semiconductor chip (FIG. 6-7: el. 112; para. 36-37); and a first bonding structure (FIG. 18A: el. 54’, 59, 154’) between the first semiconductor chip and the second semiconductor chip, wherein the first bonding structure comprises: the first upper conductive pad (FIG. 18A: el. 54; para. 40); the second lower conductive pad (FIG. 18A: el. 154; para. 40); a protective metal layer (FIG. 18A: el. 59; para. 41-43 | protective metal layer 59 formed from inter-diffusion region of fill-in metal layers 58 and 158) between the first upper conductive pad (FIG. 18A: el. 54’; para. 35, 40) and the second lower conductive pad (FIG. 18A: el. 154’; para. 38, 40 | protective metal layer 59 is formed between pads 54’ and 154’ each of which do not include the protective metal layer 59); and a diffusion barrier (FIG. 18A: el. 48, 148; para. 24, 38) surrounding the first upper conductive pad and the second lower conductive pad (Lii – FIG. 18A: el. 54, 154), wherein the protective metal layer covers a surface of the first upper conductive pad and a surface of the second lower conductive pad (FIG. 18A: el. 59, 54’, 154’; para. 35, 38, 41-43, 46), wherein the upper surface of the first semiconductor chip (FIG. 6-7, 18A: el. 42; para. 13, 22 | dielectric layer 42 forms upper surface of first semiconductor chip 4) and the lower surface of the second semiconductor chip directly contact each other (FIG. 6-7, 18A: el. 142; para. 36-37 | dielectric layer 142 forms lower surface of second semiconductor chip 112 and directly contacts dielectric layer 42 which forms the upper surface of first semiconductor chip 4), wherein the semiconductor package further comprises a first interface between the first semiconductor chip and the second semiconductor chip (FIG. 18A | first interface formed of interface between dielectric layer 42 of first semiconductor chip and dielectric layer 142 of second semiconductor chip) and a second interface between the protective metal layer and the second lower conductive pad (FIG. 18A | second interface formed of interface between protective metal layer 59 and second lower conductive pad 154’ (para. 38: sent. 4)), and wherein a first level of the first interface is equal to or lower than a second level of the second interface (FIG. 18A | first level of first interface is lower than a second level of the second interface as shown in annotated FIG. 18A, provided in Re claim 1 section). Lii also teaches a benefit of the protective metal layer is a reduction of non-coplanar dishing problems and a reduction in the pressure applied to achieve bonding (para. 3, 27, 39).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jang and Lii, to enable using the bonding structure of Lii in the semiconductor package of Jang, for the benefit of reducing bond pad dishing problems and reducing the applied bonding pressure.
The combination of Jang and Lii fails to directly disclose an intermetallic compound in the protective metal layer.
In a similar field of endeavor, Kannojia teaches forming a metal-to-metal bond between substrates by forming an intermetallic Cu-Sn compound in a protective metal layer at the interface between bond pads (pg. 6744: para. 1; pg. 6746: FIG. 2). Kannojia teaches an intermetallic compound in the protective metal layer (pg. 6744: para. 1; pg. 6746: FIG. 2). Kannojia also teaches that forming a Cu-Sn intermetallic compound in the protective metal layer results in the combined benefits of a low bonding pressure, a low bonding temperature, and the formation of a bonding material which is stable at temperatures higher than the bonding temperature, as well as a lower cost compared to an interfacial protective metal layer comprising indium and copper. (pg. 6744: para. 1; pg. 6746: para. 2).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kannojia and the teachings of the combination of Lii and Jang, to enable using the intermetallic compound of Kannojia in the protective metal layer of the bonding structure of the combination of Lii and Jang, for the combined benefits of low bonding pressures, low bonding temperatures, and low cost.
Re claim 11: The combination of Jang, Lii, and Kannojia teaches, the semiconductor package of claim 10, wherein the first semiconductor chip further comprises a first upper passivation layer (Jang - FIG. 1: el. 185; para. 32) on the upper surface of the first semiconductor chip (Jang - FIG. 1: el. 100, 185) and a first lower passivation layer (Jang - FIG. 1: el. 102; para. 23) on the lower surface of the first semiconductor chip (Jang - FIG. 1: el. 100, 102), wherein the second semiconductor chip further comprises a second lower passivation layer (Jang - FIG. 1: el. 215; para. 33) on the lower surface of the second semiconductor chip (Jang - FIG. 1: el. 200, 215), and wherein the first upper passivation layer directly contacts the second lower passivation layer (Jang - FIG. 1: el. 185, 215).
Re claim 12: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 10, further comprising a third interface between the protective metal layer and the first upper conductive pad, wherein the second interface and the third interface have a concavo-convex structure. (Lii - FIG. 18A | third interface formed of interface between protective metal layer 59 and first upper conductive pad 54’ (para. 35)), wherein the second interface and the third interface have a concavo-convex structure (Lii – para. 28 | Lii teaches that the micro recesses of FIG. 15B can happen at the same time as dishing, which results from chemical mechanical polishing, and that the micro recesses of FIG. 15B can happen on the dished structure of FIG. 15A; micro recesses are a well-known artifact of a chemical mechanical polishing process; the result of the micro recesses of FIG. 15B on the dished structure of FIG. 15A is the formation of undulations on the surface of the protective metal layer 59 of FIG. 18A, in similar form to the undulations formed in the protective metal layer 59 of FIG. 18B; the resulting structure of the protective metal layer 59 has a concavo-convex structure at the interface with second lower conductive pad 154’ (corresponding to the second interface) and first upper conductive pad 54’(corresponding to the third interface)). As an illustrative evidentiary example, Kung shows a concavo-convex structure at an interface between a protective metal layer and adjacent chemically mechanically polished copper conductive pads (“Investigation of Low-Pressure Sn-Passivated Cu-to-Cu Direct Bonding in 3D-Integration,” FIG. 8, pg. 6-7, Kung et al).
Re claim 13: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 10, wherein a thickness of a center of the protective metal layer is greater than a thickness of an edge of the protective metal layer (Lii – FIG. 18A: el. 59).
Re claim 15: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 10, wherein the protective metal layer comprises at least one of gold, silver, nickel, and tin (Kannojia - pg. 6744: para. 1; pg. 6746: para. 2 | Kannojia teaches a Cu-Sn intermetallic compound in the protective metal layer), and wherein the intermetallic compound comprises copper and at least one of gold, silver, nickel, and tin (Kannojia - pg. 6744: para. 1; pg. 6746: para. 2 | Kannojia teaches a Cu-Sn intermetallic compound in the protective metal layer).
Re claim 16: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 10, further comprising: a second bonding structure between the second semiconductor chip and the third semiconductor chip (Jang – annotated FIG. 1| second bonding structure labelled in annotated FIG. 1 provided below); a third bonding structure between the third semiconductor chip and the fourth semiconductor chip (Jang – annotated FIG. 1| third bonding structure labelled in annotated FIG. 1 provided below); and a fourth bonding structure between the fourth semiconductor chip and the fifth semiconductor chip (Jang - para. 25-26 | Jang teaches a fifth semiconductor chip in the semiconductor chip stack as Jang teaches that the plurality of semiconductor chips may be the same semiconductor chip and the plurality of semiconductor chips is not limited to four semiconductor chips. The fifth semiconductor chip, being the same as the 2nd, 3rd, and 4th semiconductor chips, has a matching bonding structure between the fourth semiconductor chip and the fifth semiconductor chip).
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Re claim 17: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 16, wherein each of the second bonding structure, the third bonding structure, and the fourth bonding structure comprises a respective protective metal layer and an intermetallic compound in the respective protective metal layer (Lii – FIG. 18A: el. 59; para. 41-43 | Lii teaches bonding structures having a protective metal layer) (Kannojia - pg. 6744: para. 1; pg. 6746: FIG. 2 | Kannojia teaches an intermetallic compound in the protective metal layer).
Re claim 18: Jang teaches a semiconductor package (FIG. 9; para. 95) comprising: a package substrate (FIG. 9: el. 1000; para. 96); an interposer substrate (FIG. 9: el. 50; para. 87) on the package substrate (FIG. 9); at least one semiconductor chip structure (FIG. 9: el. CS1; para. 96-97 | semiconductor chip structure formed of semiconductor chip stack formed on interposer 50) on the interposer substrate (FIG. 9); internal connection members connecting the interposer substrate and the at least one semiconductor chip structure (FIG. 8: el. BP; para. 83); and a mold layer at least partially covering the interposer substrate and the at least one semiconductor chip structure (FIG. 8, 9: el. 500, 450; para. 82), wherein the at least one semiconductor chip structure comprises: a first semiconductor chip (FIG. 1, 9: el. 100; para. 22-25); second semiconductor chips (FIG. 1, 9: el. 200, 300, 400; para. 25-26) on the first semiconductor chip (FIG. 1, 9), the second semiconductor chips comprising a lowermost second semiconductor chip (FIG. 1: el. 200); and a bonding structure between the first semiconductor chip and the lowermost second semiconductor chip (annotated FIG. 2: el. PAD1-1, PAD3-2 | bonding structure formed of bond pads shown in annotated FIG. 2, provided in Re claim 1 section), wherein the bonding structure comprises: a first conductive pad (annotated FIG. 2: el. PAD1-1; para. 36 | first conductive pad PAD1-1 labelled in annotated FIG. 2, provided in Re claim 1 section) on an upper surface of the first semiconductor chip (annotated FIG. 2: el. 100, PAD1-1; para. 32, 35-36); a second conductive pad (annotated FIG. 2: el. PAD3-2; para. 36 | second lower conductive pad PAD3-2 labelled in annotated FIG. 2, provided in Re claim 1 section) on a lower surface of the lowermost second semiconductor chip (annotated FIG. 2: el. 200, PAD3-2; para. 36), wherein the upper surface of the first semiconductor chip and the lower surface of the chip structure directly contact each other (FIG. 1, 2: el. 100, 200; para. 47 | upper surface of first semiconductor chip 100 in contact with lower surface of bottom semiconductor chip 200 of the chip structure). Jang fails to teach a protective metal layer between the first conductive pad and the second conductive pad; and an intermetallic compound in the protective metal layer, wherein the protective metal layer covers a surface of the first conductive pad and a surface of the second conductive pad, wherein the at least one semiconductor chip structure comprises a first interface between the first semiconductor chip and the second conductive pad and a second interface between the protective metal layer and the second conductive pad, and wherein a first level of the first interface is equal to or lower than a second level of the second interface.
In a similar field of endeavor, Lii teaches bonding stacked dies or wafers using direct metal-to-metal bonding of metal bond pads (FIG. 6, 18A, 18B; para. 25, 40, 56), and teaches a protective metal layer (FIG. 18A, 18B: el. 59; para. 41-43) between a first bond pad of an upper surface of a lower die and a second bond pad of a lower surface of an upper die (FIG. 6, 18A: el. 54, 154; para. 39-40). Lii teaches a semiconductor package (abstract) comprising: a bonding structure (FIG. 18A: el. 54’, 59, 154’) between a first semiconductor chip (FIG. 6-7: el. 4; para. 13) and a lowermost second semiconductor chip (FIG. 6-7: el. 112; para. 36-37), wherein the bonding structure comprises: a first conductive pad (FIG. 18A: el. 54; para. 40) on an upper surface of the first semiconductor chip (FIG. 6-7: el. 4; para. 13); a second conductive pad (FIG. 18A: el. 154; para. 40) on a lower surface of the lowermost second semiconductor chip (FIG. 6-7: el. 112; para. 36-37); a protective metal layer (FIG. 18A: el. 59; para. 41-43 | protective metal layer 59 formed from inter-diffusion region of fill-in metal layers 58 and 158) between the first conductive pad (FIG. 18A: el. 54’; para. 35, 40) and the second conductive pad (FIG. 18A: el. 154’; para. 38, 40 | protective metal layer 59 is formed between pads 54’ and 154’ each of which do not include the protective metal layer 59); wherein the protective metal layer covers a surface of the first conductive pad and a surface of the second conductive pad (FIG. 18A: el. 59, 54’, 154’; para. 35, 38, 41-43, 46), wherein the upper surface of the first semiconductor chip (FIG. 6-7, 18A: el. 42; para. 13, 22 | dielectric layer 42 forms upper surface of first semiconductor chip 4) and the lower surface of the chip structure directly contact each other (FIG. 6-7, 18A: el. 142; para. 36-37 | dielectric layer 142 forms lower surface of lowermost second semiconductor chip 112 of chip structure and directly contacts dielectric layer 42 which forms the upper surface of first semiconductor chip 4), wherein the at least one semiconductor chip structure comprises a first interface between the first semiconductor chip and the second conductive pad (FIG. 18A | first interface formed of interface between first conductive pad 54’ of first semiconductor chip and second conductive pad 154’) and a second interface between the protective metal layer and the second conductive pad (FIG. 18A | second interface formed of interface between protective metal layer 59 and second conductive pad 154’ (para. 38: sent. 4)), and wherein a first level of the first interface is equal to or lower than a second level of the second interface (FIG. 18A | first level of first interface is lower than a second level of the second interface as shown in annotated FIG. 18A, provided below). Lii also teaches a benefit of the protective metal layer is a reduction of non-coplanar dishing problems and a reduction in the pressure applied to achieve bonding (para. 3, 27, 39).
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Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Jang and Lii, to enable using the bonding structure of Lii in the semiconductor package of Jang, for the benefit of reducing bond pad dishing problems and reducing the applied bonding pressure.
The combination of Jang and Lii fails to directly disclose an intermetallic compound in the protective metal layer.
In a similar field of endeavor, Kannojia teaches forming a metal-to-metal bond between substrates by forming an intermetallic Cu-Sn compound in a protective metal layer at the interface between bond pads (pg. 6744: para. 1; pg. 6746: FIG. 2). Kannojia teaches an intermetallic compound in the protective metal layer (pg. 6744: para. 1; pg. 6746: FIG. 2). Kannojia also teaches that forming a Cu-Sn intermetallic compound in the protective metal layer results in the combined benefits of a low bonding pressure, a low bonding temperature, and the formation of a bonding material which is stable at temperatures higher than the bonding temperature, as well as a lower cost compared to an interfacial protective metal layer comprising indium and copper. (pg. 6744: para. 1; pg. 6746: para. 2).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kannojia and the teachings of the combination of Lii and Jang, to enable using the intermetallic compound of Kannojia in the protective metal layer of the bonding structure of the combination of Lii and Jang, for the combined benefits of low bonding pressures, low bonding temperatures, and low cost.
Re claim 19: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 18, wherein the at least one semiconductor chip structure comprises a third interface between the protective metal layer and the first conductive pad (Lii - FIG. 18A | third interface formed of interface between protective metal layer 59 and first conductive pad 54’ (para. 35)), and wherein the second interface and the third interface have a concavo-convex structure (Lii – para. 28 | Lii teaches that the micro recesses of FIG. 15B can happen at the same time as dishing, which results from chemical mechanical polishing, and that the micro recesses of FIG. 15B can happen on the dished structure of FIG. 15A; micro recesses are a well-known artifact of a chemical mechanical polishing process; the result of the micro recesses of FIG. 15B on the dished structure of FIG. 15A is the formation of undulations on the surface of the protective metal layer 59 of FIG. 18A, in similar form to the undulations formed in the protective metal layer 59 of FIG. 18B; the resulting structure of the protective metal layer 59 has a concavo-convex structure at the interface with second conductive pad 154’ (corresponding to second interface) and first conductive pad 54’(corresponding to third interface)). As an illustrative evidentiary example, Kung shows a concavo-convex structure at an interface between a protective metal layer and adjacent chemically mechanically polished copper conductive pads (“Investigation of Low-Pressure Sn-Passivated Cu-to-Cu Direct Bonding in 3D-Integration,” FIG. 8, pg. 6-7, Kung et al).
Re claim 20: The combination of Jang, Lii, and Kannojia teaches the semiconductor package of claim 18, wherein the protective metal layer comprises at least one of gold, silver, nickel, and tin (Kannojia - pg. 6744: para. 1; pg. 6746: para. 2 | Kannojia teaches a Cu-Sn intermetallic compound in the protective metal layer), and wherein the intermetallic compound comprises copper and at least one of gold, silver, nickel, and tin (Kannojia - pg. 6744: para. 1; pg. 6746: para. 2 | Kannojia teaches a Cu-Sn intermetallic compound in the protective metal layer).
Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Lii and Kannojia as applied to claims 1 and 10 above, and further in view of Hou et al. (US PGPub 20220149002 A1; hereinafter referred to as "Hou”).
Re claim 8: The combination of Jang, Lii, and Kannojia fails to teach the semiconductor package of claim 1, wherein the protective metal layer has a thickness of 0.001 to 0.01 times of a thickness of the first conductive pad and a thickness of the second conductive pad.
In a similar field of endeavor, Hou teaches bonding stacked dies using direct metal-to-metal bonding of metal bond pads (abstract) and a protective metal liner layer (FIG. 9: el. 999; para. 54), between metal bond pads (FIG. 9: el. 788, 988; para. 54), wherein the protective metal layer has a thickness of 0.1 times of a thickness of the first conductive pad and a thickness of the second conductive pad (para. 65). Hou further teaches the thickness of the protective metal liner layer as a result-effective variable for providing a desired diffusion length for forming a protective metal layer at low temperature annealing conditions (para. 17, 37, 65). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to vary, through routine optimization, the thickness of the protective metal layer relative to the thickness of the conductive bond pads, as Hou has identified the thickness of the protective metal layer as a result-effective variable. In the absence of an indication that the claimed range produces unexpected results or has criticality, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a thickness of the protective metal layer of 0.001 to 0.01 times of a thickness of the first conductive pad and a thickness of the second conductive pad, in order to achieve the desired diffusion length for forming the protective metal layer at the desired annealing conditions.
Re claim 14: The combination of Jang, Lii, and Kannojia fails to teach the semiconductor package of claim 10, wherein the protective metal layer has a thickness of 0.001 to 0.01 times of a thickness of the first upper conductive pad and the second lower conductive pad.
In a similar field of endeavor, Hou teaches bonding stacked dies using direct metal-to-metal bonding of metal bond pads (abstract) and a protective metal liner layer (FIG. 9: el. 999; para. 54), between metal bond pads (FIG. 9: el. 788, 988; para. 54), wherein the protective metal layer has a thickness of 0.1 times of a thickness of the first conductive pad and a thickness of the second conductive pad (para. 65). Hou further teaches the thickness of the protective metal liner layer as a result-effective variable for providing a desired diffusion length for forming a protective metal layer at low temperature annealing conditions (para. 17, 37, 65). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to vary, through routine optimization, the thickness of the protective metal layer relative to the thickness of the conductive bond pads, as Hou has identified the thickness of the protective metal layer as a result-effective variable. In the absence of an indication that the claimed range produces unexpected results or has criticality, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a thickness of the protective metal layer of 0.001 to 0.01 times of a thickness of the first upper conductive pad and a thickness of the second lower conductive pad, in order to achieve the desired diffusion length for forming the protective metal layer at the desired annealing conditions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art discloses direct bonded stacked die with bond pads having a protective metal layer at the bonding interface and discloses illustrative examples of a concavo-convex structure formed at the interface between a protective metal layer and a chemically mechanically polished conductive pad surface.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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