DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 2021/0057276) (hereafter Liu).
Regarding claim 1, Liu discloses a semiconductor device, comprising:
a substrate 20 (Fig. 13C, paragraph 0013);
a plurality of fins 24 (Fig. 13C, paragraph 0013) discretely arranged on the substrate 20 (Fig. 13C);
a connecting layer 42A (Fig. 14, paragraph 0023) on sidewalls of the plurality of fins 24’ (Fig. 14) and between adjacent fins, a top surface of the connecting layer 42A (Fig. 13C) being coplanar with a top surface of the plurality of fins 24’ (Fig. 14); and
a gate structure 56 (Figs. 13C and 14, paragraph 0028) across the plurality of fins 24 (Fig. 13C) and the connecting layer on the substrate 20 (Fig. 13C);
wherein: each fin 24 (Figs. 4 and 13C) of the plurality of fins includes one or more channel layers 24’ (Figs. 4 and 14) spaced apart from each other, and each of the one or more channel layers 24’ (Figs. 4 and 14) is surrounded (see Fig. 4, wherein 24’ is surrounded by 32 and 34 which are replaced with 56 in Fig. 13C and paragraph 0028) by the gate structure 56 (Figs. 13C and 14, paragraph 0028).
Regarding claim 2, Liu further discloses the device according to claim 1, wherein: the gate structure 56 (Fig. 13C) includes a gate dielectric layer 52 (Fig. 13C, paragraph 0028) and a gate electrode layer 54 (Fig. 13C, paragraph 0028) on the gate dielectric layer 52 (Fig. 13C), and each of the one or more channel layers 24’ (Figs. 4 and 14) is surrounded (see Fig. 4, wherein 24’ is surrounded by 32 and 34 which are replaced with 52 and 54 in Fig. 13C and paragraph 0028) by the gate dielectric layer 52 (Fig. 13C) and further surrounded by the gate electrode layer 54 (Fig. 13C).
Regarding claim 3, Liu further discloses the device according to claim 2, wherein: the gate dielectric layer 52 (Fig. 13C, paragraph 0029, wherein “hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like”) is made of a high-k dielectric material including at least one of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or a combination thereof.
Regarding claim 4, Liu further discloses the device according to claim 1, further comprising: an isolation structure 22 (Fig. 13C, paragraph 0013) on the substrate 20 (Fig. 13C) and between the adjacent fins 24 (Fig. 13C).
Regarding claim 5, Liu further discloses the device according to claim 4, wherein: a portion of each fin 24 (Fig. 13A) on the substrate 20 (Fig. 13A) has a top surface higher (see Fig. 13A, wherein 24’ is higher than 22) than a top surface of the isolation structure 22 (Fig. 13A), and a portion of the gate dielectric layer 52 (Figs. 13B and 13C) is formed on the portion of each fin 24’ (Fig. 13B) and on the isolation structure 22 (Fig. 13C).
Regarding claim 10, Liu further discloses the device according to claim 1, wherein: the connecting layer 42A (Fig. 6A, paragraph 0021, wherein “silicon germanium”) is made of a material including silicon germanium, amorphous carbon, amorphous germanium, or a combination thereof.
Regarding claim 11, Liu further discloses the device according to claim 1, further comprising: a protection layer 58 (Fig. 14, paragraph 0033) on the gate structure 56 (Fig. 14).
Regarding claim 12, Liu further discloses the device according to claim 11, wherein: the protection layer 58 (Fig. 14, paragraph 0033, wherein “silicon nitride, silicon oxynitride, silicon oxy-carbo-nitride, or the like”) is made of a material including at least one of silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or silicon carbonitride boride (SiCBN).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 4 above, and further in view of Young et al. (US 2021/0126099) (hereafter Young).
Regarding claim 6, Liu discloses the device according to claim 4, however Liu does not disclose each fin of the plurality of fins includes one or more sacrificial layers located between adjacent two channel layers; and a top surface of the isolation structure is flush with a bottom surface of a bottom sacrificial layer.
Young discloses each fin of the plurality of fins (111, 220, 216, 116, and 132 in Fig. 24) includes one or more sacrificial layers (220 and 132 in Fig. 24) located between adjacent two channel layers 116 (Fig. 24, paragraph 0051); and a top surface of the isolation structure 115 (Fig. 28, paragraph 0026) is flush with a bottom surface of a bottom sacrificial layer 220 (Fig. 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Liu to include each fin of the plurality of fins includes one or more sacrificial layers located between adjacent two channel layers; and a top surface of the isolation structure is flush with a bottom surface of a bottom sacrificial layer, as taught by Young, since the inner spacers/sacrificial layers 132 (Young, Fig. 24, paragraph 0046) may be referred to as a barrier for protecting the S/D regions 140 (Young, Fig. 24, paragraph 0046) from damaging during the first etching process.
Regarding claim 7, Liu in view of Young discloses the device according to claim 6, however Liu does not disclose the one or more sacrificial layers and the one or more channel layers are alternately stacked along a normal direction of a surface of the substrate.
Young discloses the one or more sacrificial layers (220 and 132 in Fig. 24) and the one or more channel layers 116 (Fig. 24, paragraph 0051) are alternately stacked along a normal direction (vertical direction in Figs. 13 and 24) of a surface of the substrate 100 (Fig. 13, paragraph 0016).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Liu to include the one or more sacrificial layers and the one or more channel layers are alternately stacked along a normal direction of a surface of the substrate, as taught by Young, since the inner spacers/sacrificial layers 132 (Young, Fig. 24, paragraph 0046) may be referred to as a barrier for protecting the S/D regions 140 (Young, Fig. 24, paragraph 0046) from damaging during the first etching process.
Regarding claim 8, Liu in view of Young discloses the device according to claim 6, however Liu does not disclose a material of the one or more sacrificial layers is different from a material of the one or more channel layers.
Young discloses a material of the one or more sacrificial layers (220 and 132 in Fig. 24; see paragraph 0059, wherein “the bottom dielectric layer 220 and the gate dielectric layer 152 have the same material”; see paragraph 0051, wherein “one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof”; and see paragraph 0036, wherein “silicon oxides, silicon nitrides, silicon carbides, silicon carbide nitride, silicon oxide carbide, silicon carbide oxynitride, and/or other suitable dielectric materials”) is different from a material of the one or more channel layers 116 (Fig. 24; and see paragraph 0020, wherein “Si layers”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Liu to include each fin of the plurality of fins includes one or more sacrificial layers located between adjacent two channel layers; and a top surface of the isolation structure is flush with a bottom surface of a bottom sacrificial layer, as taught by Young, since the inner spacers/sacrificial layers 132 (Young, Fig. 24, paragraph 0046) may be referred to as a barrier for protecting the S/D regions 140 (Young, Fig. 24, paragraph 0046) from damaging during the first etching process.
Regarding claim 9, Liu in view of Young discloses the device according to claim 8, however Liu does not disclose the material of the one or more sacrificial layers has a larger etching selection ratio than the material of the one or more channel layers.
Young discloses the material of the one or more sacrificial layers (220 and 132 in Fig. 24) has a larger etching selection ratio (see Fig. 17 and paragraph 0037) than the material of the one or more channel layers 116 (Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Liu to include the material of the one or more sacrificial layers has a larger etching selection ratio than the material of the one or more channel layers, as taught by Young, since the inner spacers/sacrificial layers 132 (Young, Fig. 24, paragraph 0046) may be referred to as a barrier for protecting the S/D regions 140 (Young, Fig. 24, paragraph 0046) from damaging during the first etching process.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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