DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group I, Species B, figures 12-15, claims 1-10 in the reply filed on September 1, 2026 is acknowledged. Accordingly, claims 11-16 are withdrawn from consideration.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 3, 2024 was considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2012/0126323 A1) (“Wu”), in view of Ju (US 2012/0228704 A1) (“Ju”), with reference to Shih et al. (US 2013/0020625 A1), in view of Brigham Young University, Electrical & Chemical Engineering, “BYU Cleanroom”, PVD Metal Depostion | BYU Cleanroom, pg. 1-5, 2019 (“BYU”), in view of V.Y. Vassiliev, “ULSI Gap Filing with a thin CVD SiO2-Based Insulator: a Review”, Russian Microelectronics, Vol. 31, No. 4, 2002, pp. 224–231. Translated from Mikroelektronika, Vol. 31, No. 4, 2002, pp. 263–273 (2002) (“Vassiliev”).
Regarding claim 1, The prior art teaches:
a semiconductor substrate (Wu 202/204);
a source region (Wu 244) formed in the semiconductor substrate (Wu 204);
a drain region (Wu 240) formed in the semiconductor substrate (Wu 204) and separated from the source region (Wu 244);
a gate dielectric film (Wu 228) formed on the semiconductor substrate (Wu 204);
a gate electrode (Wu 230) formed on the semiconductor substrate (Wu 204);
a sidewall spacer (Ju 225) formed on a side surface of the gate electrode (Ju 224/Wu 230);
a dielectric film (Wu 232; Ju 602) formed so as to contact a part of an upper surface of the gate electrode (Wu 230; Ju 224), the sidewall spacer (Ju 225) and the semiconductor substrate (It would have been obvious that based upon the combination of Wu and Ju that Wu 232 could extend to contact with the substrate Wu 202/204. An example of this obvious combination would be Shih’s figure 1B, where 191 (Equivalent to Ju 602) extends over the device an onto the substrate 151); and
a field plate electrode (Wu 234; Ju 228) formed on the dielectric film (Wu 232),
Regarding the sidewall spacers:
It would have been obvious to one of ordinary skill in the art to add the sidewall spacers of Ju to the device of Wu as the sidewall spacers will insulate the gate electrode from at least a source electrode, Wu S, that will need to be formed. Which is to say, the sidewall spacers will provide electrical and physical insulation to the gate electrode of Wu.
Regarding the limitation,
wherein a recess is formed at an upper surface of the dielectric film and between the drain region and the gate electrode, and wherein a part of the field plate electrode is buried in the recess.
BYU teaches:
That recesses are obvious/inherent in forming thin films over features. See image below.
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408
370
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Greyscale
In addition Vassiliev also teaches that these recesses are obvious/inherent in the process of forming thin films. See image below.
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572
618
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Greyscale
Therefore, in Wu when one forms 232 over 228/230 one will get the claimed recess. Then when one forms Wu 234 over 232 some of 234 will form in the recess and have a little recess itself. Therefore, it would have been obvious/inherent based upon BYU and/or Vassiliev, that when one forms the dielectric film and the field plate electrode one will obviously/inherently form the claimed recess, and the rest of the limitation will naturally/obviously follow from this.
Regarding claim 2, The prior art teaches:
wherein the dielectric film (Wu 232; Ju 602; hereinafter “A”) comprises (detailed below):
a first part (a first part of A) contacting the semiconductor substrate (Shih 191 (Equivalent to Ju 602) extends over the device an onto the substrate 151);
a second part (a second part of A) contacting the sidewall spacer (Ju 225); and
a third part (a third part of A) contacting the part of the upper surface of the gate electrode (Wu 230; Ju 224),
wherein the recess is formed at a connection point between an upper surface of the first part and an upper surface of the second part (Based upon Vassiliev and BYU the recess will be formed where there is a step (e.g. a change in elevation of the coated structure).
Regarding claim 3, The prior art teaches:
wherein a first distance between an upper surface of the semiconductor substrate (Top surface of Wu 202/204) and the recess (Wu where 232 meets 230 and 228) is greater than a thickness of the gate dielectric film (Wu 228) (this is obvious as the recess is above Wu 228 so the prior art meets the claimed distance).
Regarding claim 4, The prior art teaches:
wherein an unevenness corresponding to a surface roughness is formed at the upper surface of the first part (There will obvious be some surface roughness on the first part of A), and
wherein a first difference between the highest position of the unevenness and a lower end of the recess is greater than a second difference between the highest position of the unevenness and the lowest position of the unevenness (This is obvious based upon the claimed distances. Where it is obvious that the highest point of the surface roughness and the low point of the recess will be greater than the highest surface roughness and the lowest surface roughness).
Regarding claim 5, The prior art teaches:
wherein the first difference is greater than 2 nm (Ju ¶ 0041 where the thickness of the Ju 602 can be 10nm-50nm).
Regarding claim 6, The prior art teaches:
wherein a distance between the gate electrode (Wu 230) and the drain region (Wu 240) is greater than a distance between the gate electrode (Wu 230) and the source region (Wu 244) (this is obvious from the figures).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu, in view of Ju, with reference to Shih, in view of BYU, in view of Vassiliev, in view of Zoomer (US 5,629,552) (“Zoomer”).
Regarding claim 7, The prior art teaches:
wherein the field plate electrode (Wu 234; Ju 228) is formed of a metal silicide film (¶ 0047, where Wu 234 is formed of polysilicon; ¶¶ 0036-37, where Ju 228 is doped. However, neither Wu nor Ju state the field plate electrode is a metal silicide).
Zoomer teaches:
That fieled plate in transistors can be formed of polysilicon, Wu and Ju, or can be formed of silicides, or combinations. Col. 6 at lines 18-23.
Therefore, Zoomer teaches that silicide and polysilicon as used in a field plate electrode are art recognized equivalents for the same purpose. MPEP 2144.06-07. Therefore, it would have been obvious to one of ordinary skill in the art to replace one known material for the other.
Allowable Subject Matter
Claims 8-10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim(s) 8 is not rejected under 35 U.S.C. 103 as being unpatentable over Wu, in view of Ju, with reference to Shih, in view of BYU, in view of Vassiliev, in view of Lu et al. (US 10,756,208 B2) (“Lu”)
Regarding claim 8, Wu does not teach:
Wherein the dielectric film (Wu 232) comprises:
a first dielectric film formed so as to contact the part of the upper surface of the gate electrode, the sidewall spacer and the semiconductor substrate;
a second dielectric film formed so as to contact the other part of the upper surface of the gate electrode and the first dielectric film and to cover the gate electrode; and
a third dielectric film formed so as to contact the second dielectric film.
Lu teaches at least in figure 20:
Wherein the dielectric film (Wu 232; Lu 2002/2004) comprises:
a first dielectric film (2002) formed so as to contact the part of the upper surface of the gate electrode (108), the sidewall spacer (Ju 225) and the semiconductor substrate (Wu 202/204; Lu 102)
a second dielectric film (Lu 2302)
a third dielectric film (Lu 2304) formed so as to contact the second dielectric film (Lu 2304).
The prior art does not teach:
a second dielectric film formed so as to contact the other part of the upper surface of the gate electrode and the first dielectric film and to cover the gate electrode; and
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
