Prosecution Insights
Last updated: July 17, 2026
Application No. 18/764,060

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jul 03, 2024
Priority
Sep 20, 2023 — JP 2023-151829
Examiner
VALENZUELA, PATRICIA D
Art Unit
Tech Center
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+30.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
63 currently pending
Career history
794
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taya(USPGPUB DOCUMENT: 2018/0068918, hereinafter Taya) in view of Eguchi (USPGPUB DOCUMENT: 2018/0374817, hereinafter Eguchi). Re claim 1 Taya discloses a semiconductor device comprising: a case(6) that accommodates a semiconductor chip(3) therein; a sealing material(8) injected into the case(6); and a lid(7) fitted into an opening of the case(6), wherein the lid(7) includes a first lid(7) member Taya does not disclose wherein the lid(7) includes a first lid(7) member and a second lid(7) member that partially overlap each other, the first lid(7) member has a first notch portion and a first convex portion in a portion overlapping with the second lid(7) member, the second lid(7) member has a second notch portion and a second convex portion in a portion overlapping with the first lid(7) member, and the first lid(7) member and the second lid(7) member are combined each other with the second convex portion being inserted into the first notch portion and the first convex portion being inserted into the second notch portion. Eguchi disclose wherein the lid includes a first lid member(520/532/540 of Eguchi) and a second lid member(544/542 of Eguchi) that partially overlap each other, the first lid member(520/532/540 of Eguchi) has a first notch portion(notch of 520/532/540 of Eguchi) and a first convex portion[0075] in a portion overlapping with the second lid member(544/542 of Eguchi), the second lid member(544/542 of Eguchi) has a second notch portion(notch of 544/542 of Eguchi) and a second convex portion[0075] in a portion overlapping with the first lid member(520/532/540 of Eguchi), and the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are combined each other with the second convex portion[0075] being inserted into the first notch portion(notch of 520/532/540 of Eguchi) and the first convex portion[0075] being inserted into the second notch portion(notch of 544/542 of Eguchi). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Eguchi to the teachings of Taya in order to provide a semiconductor apparatus with improved reliability [0005, Eguchi]. The limitations “sealing material injected into the case; and a lid fitted into an opening of the case” are(is) considered to be process limitations that do not carry weight in a claim drawn to structure. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. Re claim 2 Taya and Eguchi disclose the semiconductor device according to claim 1, wherein the sealing material(8), the first lid member(520/532/540 of Eguchi), and the second lid member(544/542 of Eguchi) are integrated. Re claim 3 Taya and Eguchi disclose the semiconductor device according to claim 1, wherein the first lid member(520/532/540 of Eguchi) has a first fold-back portion that protrudes from the first convex portion[0075] toward the first notch portion(notch of 520/532/540 of Eguchi) side, the second lid member(544/542 of Eguchi) has a second fold-back portion that protrudes from the second convex portion[0075] toward the second notch portion(notch of 544/542 of Eguchi) side, and the first fold-back portion and the second fold-back portion engage with each other. Re claim 4 Taya and Eguchi disclose the semiconductor device according to claim 2, wherein the first lid member(520/532/540 of Eguchi) has a first fold-back portion that protrudes from the first convex portion[0075] toward the first notch portion(notch of 520/532/540 of Eguchi) side, the second lid member(544/542 of Eguchi) has a second fold-back portion that protrudes from the second convex portion[0075] toward the second notch portion(notch of 544/542 of Eguchi) side, and the first fold-back portion and the second fold-back portion engage with each other. Re claim 5 Taya and Eguchi disclose the semiconductor device according to claim 3, wherein a tip of at least one of the first fold-back portion and the second fold-back portion has an acute angle shape. Re claim 6 Taya and Eguchi disclose the semiconductor device according to claim 4, wherein a tip of at least one of the first fold-back portion and the second fold-back portion has an acute angle shape. Re claim 7 Taya and Eguchi disclose the semiconductor device according to claim 1, wherein the first lid member(520/532/540 of Eguchi) has a first step portion on a side of the first notch portion(notch of 520/532/540 of Eguchi) of the first convex portion[0075], the second lid member(544/542 of Eguchi) has a second step portion on a side of the second notch portion(notch of 544/542 of Eguchi) of the second convex portion[0075], and the first step portion and the second step portion are come into contact with each other. Re claim 8 Taya and Eguchi disclose the semiconductor device according to claim 2, wherein the first lid member(520/532/540 of Eguchi) has a first step portion on a side of the first notch portion(notch of 520/532/540 of Eguchi) of the first convex portion[0075], the second lid member(544/542 of Eguchi) has a second step portion on a side of the second notch portion(notch of 544/542 of Eguchi) of the second convex portion[0075], and the first step portion and the second step portion are come into contact with each other. Re claim 9 Taya and Eguchi disclose the semiconductor device according to claim 1, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 10 Taya and Eguchi disclose the semiconductor device according to claim 2, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 11 Taya and Eguchi disclose the semiconductor device according to claim 3, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 12 Taya and Eguchi disclose the semiconductor device according to claim 4, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 13 Taya and Eguchi disclose the semiconductor device according to claim 5, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 14 Taya and Eguchi disclose the semiconductor device according to claim 6, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 15 Taya and Eguchi disclose the semiconductor device according to claim 7, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Re claim 16 Taya and Eguchi disclose the semiconductor device according to claim 8, wherein the first lid member(520/532/540 of Eguchi) and the second lid member(544/542 of Eguchi) are members of a same shape. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 03, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677712
SEMICONDUCTOR PACKAGE HAVING MULTIPLE REDISTRIBUTION LAYERS AND METHOD OF MAKING THE SAME
3y 0m to grant Granted Jul 07, 2026
Patent 12677656
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 11m to grant Granted Jul 07, 2026
Patent 12672539
THIN FILM RESISTOR, THERMISTOR AND METHOD OF PRODUCING THE SAME
3y 0m to grant Granted Jun 30, 2026
Patent 12666951
SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jun 23, 2026
Patent 12666952
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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