DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0238315 A1 to Qiao et al. (hereinafter “Qiao”).
Regarding claim 1, Qiao discloses a semiconductor module comprising:
a substrate (semiconductor packaged structure 100 having circuit board 10; Fig. 1; paragraph [0035]);
at least one chip disposed on and electrically connected to the substrate (chip 20 on and electrically connected to board 10; Fig. 1; paragraph [0035]);
at least one signal assembly disposed on the substrate along a normal direction of the substrate and electrically connected to the substrate (pin 30 disposed on and electrically connected to board 10 and extending therefrom in an direction perpendicular thereto; Fig. 1; paragraph [0035]), the at least one signal assembly comprising at least one power semiconductor package signal connection element disposed on the substrate (pin 30 comprising connecting part 31 disposed on board 10; Fig. 1; paragraph [0036]) and at least one implanted signal pin inserted into the at least one power semiconductor package signal connection element (pressfit 32 disposed within part 31; Fig. 1); and
an encapsulant disposed on the substrate, having at least one groove, and covering the at least one chip and the at least one power semiconductor package signal connection element (package body 40 disposed on board 10 and having groove filled by pin 30 and board 10, where body 40 covers chip 20 and part 31; Fig. 1; paragraph [0035]), wherein the at least one groove extends from a top surface of the encapsulant relatively away from the substrate towards the substrate until at least one upper surface of the at least one power semiconductor package signal connection element is exposed (groove extends from top surface of body 40 toward board 10 such that upper surface of part 31 is exposed; Fig. 1).
Regarding claim 2, Qiao discloses the semiconductor module of claim 1, wherein a diameter of the at least one groove tapers from the top surface of the encapsulant towards the substrate (groove may be defined such that it tapers at the board 10 from the top surface of body 40; Fig. 1).
Regarding claim 3, Qiao discloses the semiconductor module of claim 1, wherein a height of the at least one power semiconductor package signal connection element is greater than a depth of the at least one groove (groove may be defined such that its depth is shorter than the height of the part 31; Fig. 1).
Regarding claim 4, Qiao discloses the semiconductor module of claim 1, further comprising: at least one connector electrically connecting between the at least one chip and the substrate (metal layer 12 electrically connecting chip 20 and board 10; Fig. 1).
Regarding claim 5, Qiao discloses a manufacturing method of a semiconductor module, comprising:
disposing at least one chip on a substrate, the at least one chip being electrically connected to the substrate (method of producing semiconductor packaged structure 100 having chip 20 on and electrically connected to circuit board 10; Fig. 1; paragraph [0035]);
disposing at least one power semiconductor package signal connection element on the substrate along a normal direction of the substrate, the at least one power semiconductor package signal connection element being electrically connected to the substrate (connection part 31 on substrate and arranged in direction perpendicular to board 10; Fig. 1; paragraph [0036]);
positioning the substrate and the at least one chip and the at least one power semiconductor package signal connection element disposed on the substrate in a lower mold (board 10, chip 20 and part 31 disposed in lower portion of packaging mold structure to form package body 40; Fig. 1);
closing an upper mold and the lower mold to form an encapsulation cavity, wherein at least one retractable mold block of the upper mold abuts on at least one upper surface of the at least one power semiconductor package signal connection element (first portion 43 and second portion of mold are adjoined together to form injection molding cavity, where first portion 43 abuts upper surface of part 31; Figs. 1 and 4; paragraph [0080]);
injecting an encapsulant into the encapsulation cavity, wherein the encapsulant is disposed on the substrate and covers the at least one chip and the at least one power semiconductor package signal connection element (body 40 formed by injection molding to cover board 10, chip 20 and part 31; Fig. 1; paragraph [0080]);
removing the upper mold and the lower mold to form at least one groove in the encapsulant, the at least one groove extending from a top surface of the encapsulant relatively away from the substrate towards the substrate until the at least one upper surface of the at least one power semiconductor package signal connection element is exposed (mold is removed to form body 40 having groove filled by pin 30 and board 10, where groove extends from top surface of body 40 toward board 10 such that upper surface of part 31 is exposed; Fig. 1); and
inserting at least one implanted signal pin into the at least one power semiconductor package signal connection element through the at least one groove, wherein the at least one power semiconductor package signal connection element and the at least one implanted signal pin define at least one signal assembly (pressfit 32 disposed within part 31 via groove, where part 31 and pressit 32 define pin 30; Fig. 1; paragraph [0036]).
Regarding claim 6, Qiao discloses the manufacturing method of the semiconductor module of claim 5, wherein a diameter of the at least one groove tapers from the top surface of the encapsulant towards the substrate (groove may be defined such that it tapers at the board 10 from the top surface of body 40; Fig. 1).
Regarding claim 7, Qiao discloses the manufacturing method of the semiconductor module of claim 5, wherein a height of the at least one power semiconductor package signal connection element is greater than a depth of the at least one groove (groove may be defined such that its depth is shorter than the height of the part 31; Fig. 1).
Regarding claim 8, Qiao discloses the manufacturing method of the semiconductor module of claim 5, further comprising: forming at least one connector before closing the upper mold and the lower mold to form the encapsulation cavity, the at least one connector electrically connecting between the at least one chip and the substrate (metal layer 12 formed prior to injection molding of body 40, where layer 12 electrically connects chip 20 and board 10; Figs. 1 and 4).
Regarding claim 9, Qiao discloses the manufacturing method of the semiconductor module of claim 5, wherein the substrate has a first surface and a second surface opposite to each other, and comprises a plurality of pins (board 10 has opposing surfaces and comprises pins 30; Fig. 1), and with the encapsulant injected into the encapsulation cavity, the encapsulant covers the first surface of the substrate and a portion of each of the pins, the portion of each of the pins being defined as an inner pin portion of each of the pins, and another portion of each of the pins protrudes outside the encapsulant, the another portion of each of the pins being defined as an outer pin portion of each of the pins (body 40 covers first surface of board 10 and portion of pins 30, where other portion of pins 30 are exposed to outside the body 40; Fig. 1).
Regarding claim 10, Qiao discloses the manufacturing method of the semiconductor module of claim 5, wherein the substrate comprises a direct bonded copper substrate, an insulated metal substrate, or an active metal bonding substrate (board 10 comprises double-sided copper substrate; paragraph [0055]).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2023/0187404 A1 to Liang, US 2015/0194373 A1 to Otremba et al., and US 2024/0203849 A1 to Fukuda et al. each discloses encapsulated semiconductor packages having related encapsulated structures and relative structural orientations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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