DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are pending in this office action.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1
Step 1: Claim 1 is directed to a product/system, which is one of the statutory categories of invention. Claim 1 is directed towards a product/system comprising of instructions to set values of D bits, based on values of M bits, wherein M is an integer greater than 0 and D is an integer greater than 0; wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of non-volatile memory.
Step 2A, Part 1 : Claim 1 recites “a processor configured to set values of D bits, based on values of M bits, wherein M is an integer greater than 0 and D is an integer greater than 0”.
The claim limitation of “configured to set values…” recited above cover a mathematical concept. For example, the “configured to set values” based on “…to set values of D bits, based on values of M bits, wherein M is an integer greater than 0 and D is an integer greater than 0” in claim 1, is a process that under broadest interpretation, covers mathematical concepts, but for the recitation of generic computer components. For example, other than the “processor”, the context of this claim encompasses in this limitation merely includes taking existing data and manipulating the data using a mathematical function and organizing this information into a new form, in which is a mathematical concept. For example, given some information at hand, a person is capable or (with the aid of paper and pen) of computing calculation by obtaining data and manipulating the data through a mathematical function and organizing this information into a new form, which is considered a mathematical concept under the ground of abstract ideas. If a claim limitations, under its broadest reasonable interpretation, covers abstract idea that includes a series of steps that recite Mathematical Concepts but for the recitation of generic computer components, then it falls within the “Mathematical Concepts” under the grouping of abstract ideas (Concepts that recite a mathematical concept including mathematical relationships, mathematical formulas or equations, and mathematical calculations)). Accordingly, the claim recites an abstract idea.
Step 2A, Part 2: This judicial exception is not integrated into a practical application. In particular, claim 1 recite the additional elements of, “…wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory”. The additional elements of using a processor to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory” is recited at a high level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim(s) does/do not include additional element that are sufficient to amount to significantly more than the judicial exception (See MPEP 2106.05(f)).
STEP 2B: The claim do not include additional elements that sufficient to amount to significantly more than judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using generic computer components to perform the necessary steps to “…wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory” is no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept (See MPEP 2106.05(f). The additional elements including, “…wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory” are recognized by the courts as well-understood, routine, and conventional activities when they are claimed in a merely generic manner (See MPEP 2106.05(d))(II)(iv) Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Employing well-known computer functions to execute an abstract idea, even when limiting the use of the idea one particular environment, does not add significantly more (See MPEP 2106.05(b)). The claim is not patent eligible.
Claim 2 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 2 recites the same abstract of claim 1. The claim recites the additional limitation of “…the processor is configured to set the values of D bits using one or more results of one or more logic operations of one or more of the values of M bits”, which is merely obtaining the results of the logic operation and then setting the values of D bits to a new form based on the gathering information from the results of the one or more logic operation of the M bits in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 3 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 3 recites the same abstract of claim 1. The claim recites the additional limitation of “The controller of claim 1, wherein D=1, D=2, or D=3“ in which merely set D bits as values of 1, 2, or 3 according the results of the logic operation further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 4 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 4 recites the same abstract of claim 1. The claim recites the additional limitation of “The controller of claim 1, wherein M=1, M=2, M=3, or M=4”, which is merely utilizing the M bits from a logic operation to obtain the values of the D bits and therefore, does not amount to significantly more.
Claim 5 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 5 recites the same abstract of claim 1. The claim recites the additional limitation of “the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits” which merely utilizing a processor to set the values of the D bits according to the results the M bits to obtain the D bits in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 6 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 6 recites the same abstract of claim 1. The claim recites the additional limitation of “…the processor is configured to set the value of at least one bit among the D bits to a negation of an exclusive disjunction of the values of two bits among the M bits” which merely utilizing a processor to set value of one bit among the D bits to a negation of an exclusive disjunction of the values of the two bits among the M bits based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 7 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 7 recites the same abstract of claim 1. The claim recites the additional limitation of “…the processor is configured to set the value of at least one bit among the D bits to a disjunction of a negation of the value of one bit among the M bits and a negation of the value of another bit among the M bits” which merely utilizing a processor to set value of the one bit among the D bits according to the disjunction of the negation of the value of the one big among the M bits and the negation of the values of another bit among the M bits based on logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 8 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 8 recites the same abstract of claim 1. The claim recites the additional limitation of “…to set the value of at least one bit among the D bits to a disjunction of the value of one bit among the M bits and a negation of the value of another bit among the M bits” which merely utilizing a processor to set the value of at least one bit among the D bits to a disjunction of the value of one bit among the M bits and a negation of the value of another bit among the M bits based on a logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 9 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 9 recites the same abstract of claim 1. The claim recites the additional limitation of “the processor is configured to set the value of at least one bit among the D bits to an exclusive disjunction of the values of two bits among the M bits” which merely utilizes the processor configured to set the value of the one bit among the D bits to an exclusive disjunction of the values of the two bits among the M bits based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 10 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 10 recites the same abstract of claim 1. The claim recites the additional limitation of “the processor is configured to set the value of at least one bit among the D bits to an exclusive disjunction of the value of a first bit and an exclusive disjunction of the value of a second bit and the value of a third bit, wherein the first bit, the second bit and the third bit are among the M bits” which merely utilizing a processor to set the values among the D bits to exclusive disjunction of the first bit and the second and third bit based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 11 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 11 recites the same abstract of claim 1. The claim recites the additional limitation of “the processor is configured to set the value of at least one bit among the D bits based on the value of only one bit among the M bits” which merely utilizing a processor to set the value of the one bit among the D bits based on the only one bit among the M bits based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 12 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 12 recites the same abstract of claim 1. The claim recites the additional limitation of “the processor is configured to set the value of at least one bit among the D bits based on the values of only two bits among the M bits” which merely utilizing a processor set the value of at least one bit among the D bits based on the values on the values of only two bits among the M bits based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 13 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 13 recites the same abstract of claim 1. The claim recites the additional limitation of “the system is a solid-state drive (SSD), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device” which merely utilizing a solid-state drive (SSD), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device to implement the instruction requested in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 14
Step 1: Claim 14 is directed to a product/system, which is one of the statutory categories of invention. Claim 14 is directed towards a product/system comprising of instructions to a controller configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0; wherein the controller comprises a processor configured to determine values of the M bits based on the values of the D bits.
Step 2A, Part 1 : Claim 14 recites “wherein the controller comprises a processor configured to determine values of the M bits based on the values of the D bits”.
The claim limitation of “configured to determine values of the M bits based on the values of the D bits” recited above cover a mathematical concept. For example, the “…configured to determine values of the M bits based on the values of the D bits” in claim 14, is a process that under broadest interpretation, covers mathematical concepts, but for the recitation of generic computer components. For example, other than the “controller” and “processor”, the context of this claim encompasses in this limitation merely includes taking existing data and manipulating the data using a mathematical function and organizing this information into a new form, in which is a mathematical concept. For example, given some information at hand, a person is capable or (with the aid of paper and pen) of computing calculation by obtaining data and manipulating the data through a mathematical function and organizing this information into a new form, which is considered a mathematical concept under the ground of abstract ideas. If a claim limitations, under its broadest reasonable interpretation, covers abstract idea that includes a series of steps that recite Mathematical Concepts but for the recitation of generic computer components, then it falls within the “Mathematical Concepts” under the grouping of abstract ideas (Concepts that recite a mathematical concept including mathematical relationships, mathematical formulas or equations, and mathematical calculations)). Accordingly, the claim recites an abstract idea.
Step 2A, Part 2: This judicial exception is not integrated into a practical application. In particular, claim 14 recite the additional elements of, “…configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0”. The additional elements of using a processor configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0 is recited at a high level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim(s) does/do not include additional element that are sufficient to amount to significantly more than the judicial exception (See MPEP 2106.05(f)).
STEP 2B: The claim do not include additional elements that sufficient to amount to significantly more than judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using generic computer components to perform the necessary steps to “…configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0” is no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept (See MPEP 2106.05(f). The additional elements including, “…configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, wherein M is an integer greater than 0 and D is an integer greater than 0” are recognized by the courts as well-understood, routine, and conventional activities when they are claimed in a merely generic manner (See MPEP 2106.05(d))(II)(iv) Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Employing well-known computer functions to execute an abstract idea, even when limiting the use of the idea one particular environment, does not add significantly more (See MPEP 2106.05(b)). The claim is not patent eligible.
Claim 15 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 15 recites the same abstract of claim 14. The claim recites the additional limitation of “The controller of claim 1, wherein D=1, D=2, or D=3“ in which merely set D bits as values of 1, 2, or 3 according the results of the logic operation further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 16 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 16 recites the same abstract of claim 14. The claim recites the additional limitation of “The controller of claim 1, wherein M=1, M=2, M=3, or M=4”, which is merely utilizing the M bits from a logic operation to obtain the values of the D bits and therefore, does not amount to significantly more.
Claim 17 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 17 recites the same abstract of claim 14. The claim recites the additional limitation of “the processor is configured to determine the value of at least one bit among the M bits as the value of one bit among the D bits” which merely determine the values of the one bit among the M bits among the D bits based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 18 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 18 recites the same abstract of claim 14. The claim recites the additional limitation of “…to determine the value of at least one bit among the M bits as an exclusive disjunction of the value of another bit among the M bits and a negation of the value of one bit among the D bits, or configured to determine the value of at least one bit among the M bits as an exclusive disjunction of the value of one bit among the D bits and a negation of the value of another bit among the M bits” which merely utilizing a processor to determine the results among the M bits from the logic operation among the M bits and the negation of the value of the D bits in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 19 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 19 recites the same abstract of claim 14. The claim recites the additional limitation of “the processor is configured to determine the value of at least one bit among the M bits based on the value of only one bit among the D bits” which merely utilizing a processor determine the value of one among the M bits based on the value of only one bit among the D bits based on logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 20 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 20 recites the same abstract of claim 14. The claim recites the additional limitation of “the processor is configured to determine the value of at least one bit among the M bits based on the values of only two bits among the D bits” which merely utilizing a processor to determine value of the one big among the M bits based on the values of the two bits among the D bits based on the logic operation in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Claim 21 is dependent on claim 14 and includes all the limitations of claim 14. Therefore, claim 21 recites the same abstract of claim 14. The claim recites the additional limitation of “the system is a solid-state drive (SSD), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device” which merely utilizing a solid-state drive (SSD), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device to implement the instruction requested in which further elaborates on the abstract idea and therefore, does not amount to significantly more.
Accordingly, claims 1-21 are rejected under 35 U.S.C 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-16, 18, and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S Patent Application Publication 2023/0012648 issued to Fitzpatrick et al. (hereinafter as "Fitzpatrick").
Regarding claim 1, Fitzpatrick teaches a controller, comprising:
A processor configured to set values of D bits, based on values of M bits (Fitzpatrick: [0029]; by generating the extra group of data from the given data having the reduced number of bits. The extra group of data can be generated to establish a predetermined relation among the groups of data to improve the reliability in retrieving data from the memory cells programmed at the predetermined number of bits per memory cell (e.g., N) {Examiner correlates the M bits as reduce number of bits and the extra group of data as D bits and the set values as generated from}), wherein M is an integer greater than 0 and D is an integer greater than 0 (Fitzpatrick: [0028]; It can be desirable in some instances to store a reduced number of bits (e.g., N−1) per memory cell in a memory device that has the circuity to program the threshold voltages of a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell. [0029]; by generating the extra group of data from the given data having the reduced number of bits. The extra group of data can be generated to establish a predetermined relation among the groups of data to improve the reliability in retrieving data from the memory cells programmed at the predetermined number of bits per memory cell (e.g., N). {Examiner correlates reduce number of bits as “M”. Where “M” = N-1) in which N must be greater than 0. Where extra group data bit D relationship is form from the reduce number of bits M = (N-1). Thus indicating that both M and D are greater than 0}));
wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory (Fitzpatrick: [0045]; The controller 115 can include a processing device 117 (e.g., processor) configured to execute instructions stored in a local memory 119. [0050]; The controller 115 and/or a memory device 130 can include a programming manager 113 configured to program threshold voltages of memory cells to store a predetermined number of bits per memory cell by generating extra data from a dataset that has a reduced number of bits per memory cell. [0068]; When it is desirable to store a reduced number of data groups (e.g., 157 to 159) in the memory cell group 131, an extra data group (e.g., 151) can be computed based on an XOR (or XNOR) operation, such that the reliability of the memory data 144 stored in the memory cells (e.g., 137 to 139) in the form of their programmed voltage thresholds. [0086]; When the TP, XP, UP and LP bits are known to have an XOR relation).
Regarding claim 2, Fitzpatrick teaches the processor is configured to set the values of D bits using one or more results of one or more logic operations of one or more of the values of M bits (Fitzpatrick: [0030]; The extra group of data can be generated based on an exclusive or (XOR) operation on the reduced number of bits (e.g., N−1). Alternatively, the inverse of the result of XOR (corresponding to XNOR on the reduced number of bits) can be used) {Examiner correlates the D bits as the extra group of data that is generated based on the results of the XOR operation (logic operation) of the reduced number of bits (one or more values of M bits)}).
Regarding claim 3, Fitzpatrick teaches D=1, D=2, or D=3 (Fitzpatrick: [0028]-[0029]; It can be desirable in some instances to store a reduced number of bits (e.g., N−1) per memory cell in a memory device that has the circuity to program the threshold voltages of a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell…by generating the extra group of data from the given data having the reduced number of bits. The extra group of data can be generated to establish a predetermined relation among the groups of data. [0042]; Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell {Examiner correlates D refers to number of bits stored per cell. When D=1 (SLC) it stores 1 bit per cell. Thus, the extra group of data which is ”D” is generated based on the reduced number of bits “M”. Reduced number of bits “M”=(N-1). Thus D=M=(N-1), where (N=2, D=1)}).
Regarding claim 4, Fitzpatrick teaches M=1, M=2, M=3, or M=4 (Fitzpatrick: [0028]; It can be desirable in some instances to store a reduced number of bits (e.g., N−1) per memory cell in a memory device that has the circuity to program the threshold voltages of a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell. [0042]; One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell {Examiner correlates reduced number of bits as “M”. Where “M” equal to “N-1”. Thus, when the user set [(N=2, M=1), (N=3, M=2), (N=4, M=3), (N=5, M=4)]}).
Regarding claim 6, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits to a negation of an exclusive disjunction of the values of two bits among the M bits (Fitzpatrick: [0030]; The extra group of data can be generated based on an exclusive or (XOR) operation on the reduced number of bits (e.g., N−1). Alternatively, the inverse of the result of XOR (corresponding to XNOR on the reduced number of bits) can be used. Programming the extra group of data with the given data at the predetermined number of bits (e.g., N) per memory cell can result in high reliability in data retrieval {Examiner correlates the negation of the exclusive disjunction based on negation of the XOR operation. The extra bit is generated based on performing XOR operation on the N-1 bits from the original bits (M Bits)}).
Regarding claim 7, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits to a disjunction of a negation of the value of one bit among the M bits and a negation of the value of another bit among the M bits (Fitzpatrick: [0030]; The extra group of data can be generated based on an exclusive or (XOR) operation on the reduced number of bits (e.g., N−1). Alternatively, the inverse of the result of XOR (corresponding to XNOR on the reduced number of bits) can be used).
Regarding claim 8, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits to a disjunction of the value of one bit among the M bits and a negation of the value of another bit among the M bits (Fitzpatrick: [0030]; The extra group of data can be generated based on an exclusive or (XOR) operation on the reduced number of bits (e.g., N−1). Alternatively, the inverse of the result of XOR (corresponding to XNOR on the reduced number of bits) can be used).
Regarding claim 9, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits to an exclusive disjunction of the values of two bits among the M bits (Fitzpatrick: [0070]; In FIG. 4 , data bit 161 is calculated by applying XOR operation 201 to data bits 163 to 165. For example, after computing the result of exclusive or of two of the data bits 163 to 165, an updated result can be obtained from the exclusive or of the result and another of the data bits 163 to 165 until all of the data bits 163 to 165 have participated in the exclusive or computations once).
Regarding claim 10, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits to an exclusive disjunction of the value of a first bit and an exclusive disjunction of the value of a second bit and the value of a third bit, wherein the first bit, the second bit and the third bit are among the M bits (Fitzpatrick: [0070]; In FIG. 4 , data bit 161 is calculated by applying XOR operation 201 to data bits 163 to 165. For example, after computing the result of exclusive or of two of the data bits 163 to 165, an updated result can be obtained from the exclusive or of the result and another of the data bits 163 to 165 until all of the data bits 163 to 165 have participated in the exclusive or computations once).
Regarding claim 11, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits based on the value of only one bit among the M bits (Fitzpatrick: [0251]; FIG. 17 illustrates an example of storing redundant information in the form of a parity bit of a codeword 504 having data bits 631, 641, . . . , 651 in the memory cell group 503. In some implementations, the data bit 621 provides an extra bit of parity information such that the combination of the data bits 631, 641, . . . , 651 and 621 provides an enlarged codeword having improved error recovery capability. [0253]; The extra bit stored in the memory cell group for a codeword in another memory cell group can be distributed over different page types).
Regarding claim 12, Fitzpatrick teaches the processor is configured to set the value of at least one bit among the D bits based on the values of only two bits among the M bits (Fitzpatrick: [0070]; In FIG. 4 , data bit 161 is calculated by applying XOR operation 201 to data bits 163 to 165. For example, after computing the result of exclusive or of two of the data bits 163 to 165).
Regarding claim 13, Fitzpatrick teaches a system, comprising the controller of claim 1, wherein the system is a solid-state drive (SSD), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device (Fitzpatrick: [0033]; A memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD)).
Regarding claim 14, Fitzpatrick teaches a controller configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory (Fitzpatrick: [0029]; by generating the extra group of data from the given data having the reduced number of bits. The extra group of data can be generated to establish a predetermined relation among the groups of data to improve the reliability in retrieving data from the memory cells programmed at the predetermined number of bits per memory cell (e.g., N) {Examiner correlates the M bits as reduce number of bits and the extra group of data as D bits and the set values as generated from}), wherein
M is an integer greater than 0 and D is an integer greater than 0 (Fitzpatrick: [0028]; It can be desirable in some instances to store a reduced number of bits (e.g., N−1) per memory cell in a memory device that has the circuity to program the threshold voltages of a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell. [0029]; by generating the extra group of data from the given data having the reduced number of bits. The extra group of data can be generated to establish a predetermined relation among the groups of data to improve the reliability in retrieving data from the memory cells programmed at the predetermined number of bits per memory cell (e.g., N). {Examiner correlates reduce number of bits as “M”. Where “M” = N-1) in which N must be greater than 0. Where extra group data bit D relationship is form from the reduce number of bits M = (N-1). Thus indicating that both M and D are greater than 0})); wherein
the controller comprises a processor configured to determine values of the M bits based on the values of the D bits (Fitzpatrick: [0030]; The extra group of data can be generated based on an exclusive or (XOR) operation on the reduced number of bits (e.g., N−1). Alternatively, the inverse of the result of XOR (corresponding to XNOR on the reduced number of bits) can be used. [0070]; In FIG. 4 , data bit 161 is calculated by applying XOR operation 201 to data bits 163 to 165. For example, after computing the result of exclusive or of two of the data bits 163 to 165 {Examiner correlates the values of determining the M bits based on the results of the values of the D bits based on XOR operation in such by evaluating the results of the exclusive of two of the data baits that is obtain based on generating based on the reduced number of bits that was obtained from the XOR operation}).
Regarding claim 15, Fitzpatrick teaches D=1, D=2, or D=3 (Fitzpatrick: [0028]-[0029]; It can be desirable in some instances to store a reduced number of bits (e.g., N−1) per memory cell in a memory device that has the circuity to program the threshold voltages of a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell…by generating the extra group of data from the given data having the reduced number of bits. The extra group of data can be generated to establish a predetermined relation among the groups of data. [0042]; Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell {Examiner correlates D refers to number of bits stored per cell. When D=1 (SLC) it stores 1 bit per cell. Thus, the extra group of data which is ”D” is generated based on the reduced number of bits “M”. Reduced number of bits “M”=(N-1). Thus D=M=(N-1), where (N=2, D=1)}).
Regarding claim 16, Fitzpatrick teaches M=1, M=2, M=3, or M=4 (Fitzpatrick: [0028]; It can be desirable in some instances to store a reduced number of bits (e.g., N−1) per memory cell in a memory device that has the circuity to program the threshold voltages of a group of memory cells to store a predetermined number of bits (e.g., N) per memory cell. [0042]; One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell {Examiner correlates reduced number of bits as “M”. Where “M” equal to “N-1”. Thus, when the user set [(N=2, M=1), (N=3, M=2), (N=4, M=3), (N=5, M=4)]}).
Regarding claim 18, Fitzpatrick teaches the processor is configured to determine the value of at least one bit among the M bits as an exclusive disjunction of the value of another bit among the M bits and a negation of the value of one bit among the D bits, or configured to determine the value of at least one bit among the M bits as an exclusive disjunction of the value of one bit among the D bits and a negation of the value of another bit among the M bits (Fitzpatrick: [0030]; The extra group of data can be generated based on an exclusive or (XOR) operation on the reduced number of bits (e.g., N−1). Alternatively, the inverse of the result of XOR (corresponding to XNOR on the reduced number of bits) can be used).
Regarding claim 20, Fitzpatrick teaches the processor is configured to determine the value of at least one bit among the M bits based on the values of only two bits among the D bits (Fitzpatrick: [0070]; In FIG. 4 , data bit 161 is calculated by applying XOR operation 201 to data bits 163 to 165. For example, after computing the result of exclusive or of two of the data bits 163 to 165).
Regarding claim 21, Fitzpatrick teaches a system, comprising the controller of claim 14, wherein the system is a solid-state drive (SSD), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device (Fitzpatrick: [0033]; A memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S Patent Application Publication 2023/0012648 issued to Fitzpatrick et al. (hereinafter as "Fitzpatrick") in view of U.S Patent 11,205,495 issued to Khayat et al. (hereinafter as "Khayat").
Regarding claim 5, Fitzpatrick teaches claimed invention substantially as claimed, however, Fitzpatrick does not explicitly teach the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits.
Khayat teaches the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits (Khayat: Col 3, lines 49-51; For example, the data can be retrieved from the memory cells and rewritten into the memory cells or written into another group of memory cells. Col 6, lines 15-21; The logic operation of XOR ( exclusive or ) of the two sets of data at the both sides… The result of the XOR operation can be used as soft bit data…).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify Fitzpatrick (teaches a system for to set values of D bits, based on values of M bits, wherein M is an integer greater than 0 and D is an integer greater than 0; wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of non-volatile memory) with the teachings of Khayat (teaches the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits). One of ordinary skill in the art would have been motivated to make such a combination of provide better improvement in reducing the time to responding to the request for the memory system (See Khayat: Col 13, lines 15). In addition, the references (Fitzpatrick, and Khayat) teach features that are directed to analogous art and they are directed to the same field of endeavor as Fitzpatrick, and Khayat are directed to memory systems and storing bits pertaining to memory cells.
Regarding claim 17, Fitzpatrick teaches claimed invention substantially as claimed, however, Fitzpatrick does not explicitly teach the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits.
Khayat teaches the processor is configured to determine the value of at least one bit among the M bits as the value of one bit among the D bits (Khayat: Col 3, lines 49-51; For example, the data can be retrieved from the memory cells and rewritten into the memory cells or written into another group of memory cells. Col 6, lines 15-21; The logic operation of XOR ( exclusive or ) of the two sets of data at the both sides… The result of the XOR operation can be used as soft bit data…).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify Fitzpatrick (teaches a system for to set values of D bits, based on values of M bits, wherein M is an integer greater than 0 and D is an integer greater than 0; wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of non-volatile memory) with the teachings of Khayat (teaches the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits). One of ordinary skill in the art would have been motivated to make such a combination of provide better improvement in reducing the time to responding to the request for the memory system (See Khayat: Col 13, lines 15). In addition, the references (Fitzpatrick, and Khayat) teach features that are directed to analogous art and they are directed to the same field of endeavor as Fitzpatrick, and Khayat are directed to memory systems and storing bits pertaining to memory cells.
Regarding claim 19, Fitzpatrick teaches claimed invention substantially as claimed, however, Fitzpatrick does not explicitly teach the processor is configured to determine the value of at least one bit among the M bits based on the value of only one bit among the D bits.
Khayat teaches the processor is configured to determine the value of at least one bit among the M bits based on the value of only one bit among the D bits (Khayat: Col 3, lines 49-51; For example, the data can be retrieved from the memory cells and rewritten into the memory cells or written into another group of memory cells. Col 6, lines 15-21; The logic operation of XOR ( exclusive or ) of the two sets of data at the both sides… The result of the XOR operation can be used as soft bit data…).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify Fitzpatrick (teaches a system for to set values of D bits, based on values of M bits, wherein M is an integer greater than 0 and D is an integer greater than 0; wherein the controller is configured to write the values of D bits and the values of M bits into a memory cell of non-volatile memory) with the teachings of Khayat (teaches the processor is configured to set the value of at least one bit among the D bits to the value of one bit among the M bits). One of ordinary skill in the art would have been motivated to make such a combination of provide better improvement in reducing the time to responding to the request for the memory system (See Khayat: Col 13, lines 15). In addition, the references (Fitzpatrick, and Khayat) teach features that are directed to analogous art and they are directed to the same field of endeavor as Fitzpatrick, and Khayat are directed to memory systems and storing bits pertaining to memory cells.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S Patent Application Publication 2023/0359388 issued to Nguyen et al. (hereinafter as “Nguyen”) teaches memory array comprising memory cells coupled to a plurality of wordlines where the controller perform operations receiving metadata values characterizing threshold voltage distribution.
U.S Patent Application Publication 2020/0363989 issued to Li et al. (hereinafter as “Li”) teaches memory devices with a 3D NAND memory array having a plurality of pages that includes on-die cache coupled to the memory array on the same chip and configured to cache a plurality of batches of program data.
U.S Patent Application Publication 2019/0361614 issued to NATARAJAN et al. (hereinafter as “NATARAJAN”) teaches write performance of block-based multi-level cell non-volatile memory to be increased through the use of an internal copy of blocks with a high validity.
U.S Patent Application Publication 2019/0102083 issued to Dusija et al. (hereinafter as “Dusija”) teaches storing data in multi-level cell (MLC) flash memory and determining the data storage system that has a data path to enable flash memory data access that has more graceful degradation.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW N HO whose telephone number is (571)270-0590. The examiner can normally be reached Tuesday and Thursday 10:00-6:00.
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3/9/2026
/ANDREW N HO/Examiner
Art Unit 2169
/SHERIEF BADAWI/Supervisory Patent Examiner, Art Unit 2169