Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 23, 2026.
Status of claims to be treated in this office action:
a. Independent: 1,13
b. Pending: 1-3, 5-14, 16-20
Claims 1, 2, 5-7, 10, 13, and 16-18 have been amended and claims 4 and 15 have been canceled.
Specification
The new title has been reviewed and accepted by the Examiner.
Most of the amendments to the Specification have been reviewed and are accepted by the Examiner. Those objections to the Specification are withdrawn. However, part of item 9 and part of item 11 from the previous office action filed January 14, 2026, included below and updated for clarity, have not been addressed:
Regarding para. [0049] of the “Description of the Embodiments” section, on p.10, lines 16-17, make the following change:
“The OTP circuit 210a, which is an example of the non-volatile memory, is configured to store the information required for the memory units 222…”
Further regarding para. [0051], revise the following sentence for grammar and clarity as follows:
“FIGs. 4A-4C illustrate operation modes that the stacked memory device can perform according to [[the]]an embodiment of the invention.”
The disclosure is also objected to because of the following informalities:
In para. [0007], on line 13 of p.3 of the Specification filed February 23, 2026, “memory data” has been amended to “the memory data”. Examiner asserts this should be changed to “[[the]] memory data” or “[[the]] a memory data” since it is the first instance of “memory data” in the Specification.
In para. [0049], make the following changes:
“According to the embodiment of the invention, some of the circuits for these functions of the peripheral module 226 are transferred to the logic chip 210.”
In para. [0052], make the following changes:
“For example, the logic circuit 210e sends a reset command to the GPUC 210b, the plurality of shifters 210c and the plurality of memory units 222 (paths 241, 242, 244a in FIG. 2)…The GPCU 210b sends a command to the OTP circuit 210a, and the OTP circuit 210a provide the OTP information to the GPCU 210b, and then to the memory units 222”
In para. [0053], make the following change:
“As a result, after the OTP information is sent to the memory units 222, the GPCU 210b is automatically in the standby mode until the power is turned off.”
In para. [0067], make the following changes:
“As described above, when entering the user mode, the GPCU memory test mode or OTP operation mode, the [[rest]]reset procedure is first performed after the power of the stacked memory device is turned on. When the [[rest]]reset procedure is performed”
In para. [0069], make the following change:
“the shifters 210c are not operating”
In para. [0070], make the following changes:
“The GPCU 210b and the shifters 210c are [[no]]not they have a standby status) in the normal mode.”
Appropriate correction is required.
Claim Objections
Most of the claim objections are withdrawn pursuant to claim amendments. However, claim objections 2 and 8 from the previous office action filed January 14, 2026, which are in regard to claims 1 and 13, respectively, have not been fully addressed. They are included below, updated for clarity:
Claims 1 and 13 from the claim set filed February 23, 2026 are objected to because of the following informalities:
Regarding claim 1, in the third line from the bottom of p.10, make the following change:
“plurality of shifters respectively, and the plurality of memory units respectively; and”
Regarding claim 13, on the seventh line of p.13, make the following change:
“ a memory chip with a plurality of memory units, a logic chip[[,]] bonded…”
Also, claims 1 and 13 are objected to because of the following informalities:
Regarding claim 1, add an “and” before the limitation that starts with “wherein the stacked memory device is configured to perform a reset procedure”.
Regarding claim 13, add an “and” before the limitation that starts with “wherein after the reset procedure is finished, the peripheral controller is configured to read the operation information”.
Appropriate corrections are required.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-14, and 16-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Lynch et al. (US Pub. 20040085818 A1; “Lynch”), and Shirakawa (US Pub. 20160343445 A1). Lynch paras. [0102], [0107], and [0113], and Fig. 12; and Shirakawa paras. [0117] and [0138] are relevant to claims 1 and 13.
Examiner agrees with:
The argument on p.23 that Alsop does not disclose the limitation that contains “to transfer the memory command…a shift amount with respect to a clock signal”, and
The argument on pp.21-22 that Zhou does not disclose the last limitation of claim 1, which was added via amendment.
However, the argument on pp.22-23 that neither Alsop nor Morishita disclose “a non-volatile memory circuit, configured to store operation information of the plurality of memory units” is not persuasive. Examiner notes that Morishita was not used in the previous Office Action to reject this limitation, and Examiner asserts that para. [0103] of Alsop indeed teaches this limitation. Regardless, Examiner has used Shirakawa to reject this limitation.
Claim Rejections - 35 USC § 112
The rejection of claim 1 under 35 U.S.C. 112(b) has been withdrawn pursuant to claim amendments.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 13, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Examiner acknowledges that the Applicant has amended paras. [0012], [0019], and [0023] in an effort to remedy the 112(b) rejections, however the claims are still indefinite. The paragraphs now recite a “non-volatile memory circuit operation mode,” but like “non-volatile memory operation mode”, “non-volatile memory circuit operation mode” is not defined in the spec. The metes and bounds of a “non-volatile memory circuit operation mode” are unclear. Para. [0051] describes Figs. 4A-4C, which illustrate modes, but use different names for these modes. Is the “non-volatile memory circuit operation mode” the same as the “second test mode (GPCU OTP operation mode)”? If so, the disclosure must be amended to clarify this.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (CN 113934375 A) in view of Morishita et al. (US Pub. 20050156616 A1; “Morishita”), Lynch et al. (US Pub. 20040085818 A1; “Lynch”), and Shirakawa (US Pub. 20160343445 A1).
Regarding independent claim 1, Zhou discloses a stacked memory device (Fig. 2: three-dimensional integrated chip; [n0023]), comprising:
a memory chip (memory wafer 220; [n0023]), having a plurality of memory units ([n0029]: the memory wafer is divided into several memory array blocks);
a logic chip (SSD controller wafer 210; [n0023]), bonded to the memory chip in a face-to-face manner ([n0025]: The SSD controller wafer 210 and multiple memory wafers 220 are bonded together through a three-dimensional heterogeneous integration method…Specifically, the memory wafer 220 includes multiple first three-dimensional integrated ports, and the SSD controller wafer 210 includes multiple second three-dimensional integrated ports. The memory wafer 220 (i.e., the first memory) and the SSD controller wafer are integrated on different wafers and are three-dimensionally heterogeneously connected to the first three-dimensional integrated ports through the second three-dimensional integrated ports); and
an external port module, having a plurality of external ports and coupled to the memory chip ([n0030]: As shown in Figure 3, the memory controller 330 is heterogeneously integrated with the storage array (i.e., storage wafer) 350 through a three-dimensional heterogeneous integration port located in the cache module 340. The memory controller 330 is located in the SSD controller wafer; [n0031]: It should be understood that these three-dimensional heterogeneous ports can also be located in other modules. Examiner concludes that ports could be located in a structure that is external to the SSD controller wafer and the memory wafer/chip, and may be connected to both the SSD controller wafer and the memory wafer/chip),
wherein the logic chip (Fig. 2: 210) further comprises:
a non-volatile memory circuit (Fig. 3: storage array 350; [n0041]: three-dimensional integrated storage array 350…in the SSD controller 300. Examiner asserts that SSD controller 300 is analogous to SSD controller wafer 210 of Fig. 2. SSDs are non-volatile),
a memory controller (Fig. 3: NVM controllers (i.e., second storage controllers) 380; [n0033]), coupled to the plurality of memory units and configured to control operations of memory chip ([n0036]: the bottommost NVM controller 380 among multiple off-chip NVM 302 can form another data access channel. Per [n0036] and Fig. 3, the NVM controllers 380 are connected to the off-chip NVM 302, which is analogous to memory wafer 220. Thus, Examiner concludes that 380 controls 302);
a peripheral controller (Fig. 3: DMA module 320; [n0036]), coupled to the memory controller, the non-volatile memory circuit, the plurality of memory units and the external port module ([n0029]: the DMA module (direct memory access module) in the SSD controller accesses each memory array block through the memory controller MC, which improves the parallelism of data access. Furthermore, the memory wafer includes multiple first memories, and each first memory corresponds to a memory controller (MC). The DMA module within the SSD controller accesses each first memory through the memory controller (MC), further improving the parallelism of data access);
Zhou does not explicitly disclose:
a logic chip, bonded to the memory chip in a face-to-face manner; and
an external port module, having a plurality of external ports and coupled to the memory chip,
a memory circuit, configured to store operation information of the plurality of memory units;
a plurality of shifters, coupled to the memory controller, the peripheral controller, the external port module, and the plurality of memory units respectively, each of the plurality of shifters being configured to receive a memory command, memory data and a memory address from the peripheral controller, and to transfer the memory command, the memory data and the memory address to each of the memory units respectively with a shift amount with respect to a clock signal; and
a plurality of selectors, coupled to the memory controller, the peripheral controller, the plurality of shifters respectively, and plurality of memory units respectively,
wherein when the stacked memory device is in an operation status, the peripheral controller is in a standby status, and wherein when the stacked memory device enters a memory test mode, the peripheral controller is configured to perform a memory test or control of the non-volatile memory circuit;
wherein the stacked memory device is configured to perform a reset procedure after the stacked memory device is powered on, and after the reset procedure is finished, the peripheral controller is configured to read the operation information stored in the non-volatile memory circuit, and to transfer the operation information to each of the plurality of memory units of the memory chip.
However, Morishita teaches:
a logic chip (Fig. 10: logic chip 1; [0070]), bonded to the memory chip in a face-to-face manner ([0032]: the logic chip 1 and the memory chip 2 are semiconductor chips which constitute the integrated circuit device 10 configured using the Chip-on-Chip SiP technology; [0003]: The SiP involves a Chip-on-Chip (COC) structure, which includes a plurality of semiconductor chips in such a way that a semiconductor chip stacked on top of another semiconductor chip. For example, in the Chip-on-Chip SiP, two semiconductor chips are connected by face-down bonding, with their circuit surfaces facing each other); and
an external port module (Fig. 12: tester 4; [0074]), having a plurality of external ports and coupled to the memory chip ([0074]: When testing the memory chip 2 in the SiP, the tester 4 probes the logic external I/O pad 113 to make an electrical connection; [0044]: The memory I/O pads 122 and the logic COC I/O pads 112 may be pads for inputting a signal from an external device, pads for outputting a signal to an external device…Some of the test pads 121 and the test pads 111 may serve just like the memory I/O pads 122 and the logic COC I/O pads 112 after the integrated circuit device is completed; [0075]: The tester 4 inputs a clock for testing and a data writing address and reading address to the test control circuit 13 via the logic external I/O pad 113. The test control circuit 13 transfers the clock and address from the tester 4 to the memory BIST circuit 3 via the logic COC I/O pad 112 and the memory I/O pad 122. Examiner concludes that the tester 4 is coupled to the memory chip),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Morishita to Zhou wherein the memory device comprises a logic chip, bonded to the memory chip in a face-to-face manner; and an external port module, having a plurality of external ports and coupled to the memory chip in order to reduce the parasitic capacitance between the logic chip and memory chip during testing of the face-to-face package (Morishita, [0083]).
Also, through Lynch:
a plurality of shifters (Fig. 12: shift registers 96; [0094]), coupled to the memory controller (Fig. 12 indicated that the circuitry of Fig. 12 is connected to the controller, and a controller 31 is illustrated and described in Fig. 3 and para. [0040]), the peripheral controller (Fig. 12: test selector 86; [0099]), the external port module (Write T-Portal 82; [0101]), and the plurality of memory units (memory devices 10; [0110]) respectively, each of the plurality of shifters being configured to receive a memory command, memory data and a memory address ([0113]: header data (HD) (e.g., a destination address) is provided to the read selector 90 for the chain that is to be read. The header data is then clocked through the chain of arrays 98 and output to the selector 94. The read data is then synchronously loaded from the memory devices 10 in the chain into the corresponding shift register array 12. The data is then clocked through the chain of shift registers 96) from the peripheral controller, and to transfer the memory command, the memory data and the memory address to each of the memory units respectively with a shift amount with respect to a clock signal ([0102]: the data is sent to the appropriate chain of shift registers 96 associated with the memory device 10. The write data is then clocked into the chain of shift registers where it is clocked through until it is loaded into the shift register array 12 corresponding to the memory device 10 to which the data is to be written); and
a plurality of selectors (selectors 90-1 and 90-2; [0099]), coupled to the memory controller, the peripheral controller, the plurality of shifters respectively, and plurality of memory units respectively (see mapping above), wherein when the stacked memory device is in an operation status, the peripheral controller is in a standby status ([0102]: When the memory device 10 is ready to receive the write data, the data is passed to the test selector 86, which, because this is a writing operation, is set to pass the Write Data WD to the write switch (router) 88),
and wherein when the stacked memory device enters a memory test mode, the peripheral controller is configured to perform a memory test or control of the non-volatile memory circuit ([0107]: A test operation for the embodiment of FIG. 12 will now be described…When testing the system, a Test select signal is sent to the write/test selector 86 that directs the selector to begin sending test data to the write switch 88);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lynch to modified Zhou wherein the device includes a plurality of shifters, coupled to the memory controller, the peripheral controller, the external port module, and the plurality of memory units respectively, each of the plurality of shifters being configured to receive a memory command, memory data and a memory address from the peripheral controller, and to transfer the memory command, the memory data and the memory address to each of the memory units respectively with a shift amount with respect to a clock signal; and a plurality of selectors, coupled to the memory controller, the peripheral controller, the plurality of shifters respectively, and plurality of memory units respectively, wherein when the stacked memory device is in an operation status, the peripheral controller is in a standby status, and wherein when the stacked memory device enters a memory test mode, the peripheral controller is configured to perform a memory test or control of the non-volatile memory circuit in order to provide methods and systems that improve speed and bandwidth capabilities (Lynch, [0002]-[0080]).
Also, through Shirakawa:
a memory circuit (Fig. 1: random access memory (RAM); [0047]: memory controller 20 includes a random access memory (RAM)), configured to store operation information of the plurality of memory units ([0128]: a failure table storing information on the bad blocks is generated in the RAM of the memory controller 20);
wherein the stacked memory device ([0003]: as an approach to improving the bit density of a NAND flash memory, a memory using a stacked NAND flash memory in which memory cells are stacked, a so-called bit-cost scalable (BiCS) flash memory, is being proposed) is configured to perform a reset procedure after the stacked memory device is powered on, and after the reset procedure is finished, the peripheral controller is configured to read the operation information stored in the memory circuit ([0138]: The memory controller 20 reads data in the managed region 11b after the completion of the power-on reset process. Examiner notes that the following shows that the bad block operation information is communicated between memory circuit RAM and managed region 11b, so [0138] teaches the above limitation. Per para. [0117]: the address of the logical block failed the writing or erasing is retained, for example, in a RAM of the memory controller 20 as acquired bad block information. The controller 20 registers this address in a managed region 11b in the memory cell array. Additionally, it is common practice to do power-on reset followed by reading configuration parameters and perform operations accordingly), and to transfer the operation information to each of the plurality of memory units of the memory chip ([0103]: After all of the information is transferred to the data latch circuit, the data in the data latch circuit is programmed to the ROM fuse region 11a of the memory cell array 11 (S37); [0117]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Shirakawa to modified Zhou wherein the stacked memory device contains a memory circuit, configured to store operation information of the plurality of memory units; and wherein the stacked memory device is configured to perform a reset procedure after the stacked memory device is powered on, and after the reset procedure is finished, the peripheral controller is configured to read the operation information stored in the non-volatile memory circuit, and to transfer the operation information to each of the plurality of memory units of the memory chip in order to implement a BiCS flash memory device with a reduced chip area (Shirakawa, [0123]]).
Regarding claim 5, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. Zhou does not disclose:
wherein when the stacked memory device enters the memory test mode,
the peripheral controller is further configured to receive the memory command, the memory data and the memory address from an external source via the external port module, and transfer the memory command, the memory data and the memory address to the plurality of shifters,
the plurality of shifters is configured to transfer the memory command, the memory data and the memory address to the memory units of the memory chip, and
after the plurality of memory units of the memory chip perform operations based on the memory command, the memory data and the memory address, the plurality of memory units transfer results of the operations to the peripheral controller through the plurality of shifters.
However, Morishita teaches:
wherein in a case that the stacked memory device enters a memory test mode ([0074]: When testing the memory chip 2 in the SiP, the tester 4 probes the logic external I/O pad 113),
the peripheral controller (Fig. 9B: test control circuit 13; [0067]) is further configured to receive the memory command, the memory data and the memory address from an external source via the external port module (Fig. 12: tester 4 is the external port module; [0075]: The tester 4 inputs a clock for testing and a data writing address and reading address to the test control circuit 13 via the logic external I/O pad 113), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Morishita to modified Zhou wherein in a case that the stacked memory device enters a memory test mode, the peripheral controller is further configured to receive the memory command, the memory data and the memory address from an external source via the external port module in order to reduce the parasitic capacitance between the logic chip and memory chip during testing of the face-to-face package (Morishita, [0083]).
Also, Lynch teaches:
transfer the memory command, the memory data and the memory address to the plurality of shifters ([0113]),
the plurality of shifters is configured to transfer the memory command, the memory data and the memory address to the memory units of the memory chip ([0102]), and
after the plurality of memory units of the memory chip perform operations based on the memory command, the memory data and the memory address ([0102]; [0113]), the plurality of memory units transfer results of the operations to the peripheral controller through the plurality of shifters (Abstract: data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lynch to modified Zhou wherein the peripheral controller transfers the memory command, the memory data and the memory address to the plurality of shifters, the plurality of shifters is configured to transfer the memory command, the memory data and the memory address to the memory units of the memory chip, and after the plurality of memory units of the memory chip perform operations based on the memory command, the memory data and the memory address, the plurality of memory units transfer results of the operations to the peripheral controller through the plurality of shifters in order to provide methods and systems that improve speed and bandwidth capabilities (Lynch, [0002]-[0080]).
Regarding claim 6, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. The first limitation of claim 6 is not well defined, per the 112(b) rejection of claims 6, 13, and 17, and the Examiner will interpret it as meaning that the device is operating on the non-volatile memory, as opposed to being in a refresh or standby mode. This is a normal operation mode, which is known in the art. The second limitation of claim 6 has the same meaning as the following clause from the second to last limitation of cl1: “the peripheral controller is configured to…control of the non-volatile memory circuit.” Thus, claim 6 is rejected for the same reasons.
Regarding claim 9, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. Neither Zhou nor Morishita disclose:
wherein each of the plurality of selectors is a multiplexer.
However, Lynch teaches:
wherein each of the plurality of selectors is a multiplexer ([0115]: With more selector circuitry, it is possible to join any two D-Portals together in series. This can be done to, for example, multiplex data from two files).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Alsop to modified Zhou wherein each of the plurality of selectors is a multiplexer in order to provide methods and systems that improve speed and bandwidth capabilities (Lynch, [0002]-[0080]).
Regarding claim 12, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1, and further through Zhou:
wherein the stacked memory device is a stacked DRAM device ([n0027]: Preferably, the memory wafer 220 can be a dynamic random access memory wafer or a dynamic random access memory chip.).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (CN 113934375 A), Morishita (US Pub. 20050156616 A1), Lynch (US Pub. 20040085818 A1), and Shirakawa (US Pub. 20160343445 A1) as applied to claim 1 above, and further in view of Farmwald et al. (US Pub. 20050141332 A1; “Farmwald”).
Regarding claim 2, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1, and further through Zhou:
in a case that the stacked memory device (Fig. 2: three-dimensional integrated chip; [n0023]) in the operation status ([n0014]: the SSD controller wafer further includes a cache module, the cache module being configured to convert the operating voltage of the memory controller into the operating voltage of the plurality of first memories or the operating voltage of the plurality of first memories into the operating voltage of the memory controller when the memory controller performs storage access on the plurality of first memories. Examiner concludes that the device must be in an operation status when the operating voltage is controlled), the memory controller (Fig. 3: 380) is configured to control the memory units of the memory chip ([n0036]).
Neither Zhou, Morishita, Lynch, nor Shirakawa discloses:
wherein the stacked memory device is configured to perform a reset procedure after the stacked memory device is powered on, and
However, Farmwald teaches:
wherein the stacked memory device ([0114]: a simple 3-D package, whereby the devices are stacked) is configured to perform a reset procedure after the stacked memory device is powered on ([0048]: Most of these registers can be modified and preferably are set as part of an initialization sequence that occurs when the system is powered up or reset), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Farmwald to modified Zhou wherein the stacked memory device is configured to perform a reset procedure after the stacked memory device is powered on in order to reduce power consumption while also increasing circuit density in the device (Farmwald, [0026]).
Regarding claim 3, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. Zhou discloses a memory controller, a peripheral controller, and a plurality of memory units, but neither Zhou, Morishita, Lynch, nor Shirakawa explicitly discloses:
wherein in the reset procedure, the memory controller sends a reset command to the peripheral controller, the plurality of shifters and the plurality of memory units.
However, Farmwald teaches:
wherein in the reset procedure, the memory controller sends a reset command to the peripheral controller ([0125]: Other devices, generically referred to as peripheral devices, including disk controllers, video controllers or I/O devices can also be attached to either the transceiver bus or a primary bus unit, as desired; [0102]: [0102] To reset all devices on a bus, a master sets the ResetIn line of the first device to a "1" for long enough to ensure that all devices on the bus have been reset), the plurality of shifters ([0103]: For instance, a series of sequential numbers could be clocked along the ResetIn line and at a certain time each device could be instructed to latch the current reset shift register value into the device ID register) and the plurality of memory units ([0059]: there is one other line (ResetIn, ResetOut) connecting each device in series for use during initialization to assign every device in the system a unique device ID number; [0099]: The master provides a series of unique device ID numbers for each unique device connected to the bus system…The configuration master should check each memory device and set all appropriate memory address registers).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Farmwald to modified Zhou wherein in the reset procedure, the memory controller sends a reset command to the peripheral controller, the plurality of shifters and the plurality of memory units in order to reduce power consumption while also increasing circuit density in the device (Farmwald, [0026]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (CN 113934375 A), Morishita (US Pub. 20050156616 A1), Lynch (US Pub. 20040085818 A1), and Shirakawa (US Pub. 20160343445 A1) as applied to claim 1 above, and further in view of Smith (US Pub. 20190205244 A1).
Regarding claim 7, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. Neither Zhou, Morishita, Lynch, nor Shirakawa discloses:
wherein when a memory direct test mode is entered,
the plurality of memory units is configured to directly receive the memory command, the memory data and the memory address from an external source via the external port module without using the peripheral controller to detect failure bit addresses of each of the plurality of memory units.
However, Smith teaches:
wherein in a case that a memory direct test mode is entered ([1156]: In one embodiment, for example, a stacked memory package (e.g. logic chip in a stacked memory package, etc.) may trigger and/or otherwise initiate, control, command, etc. state capture, saving of state, storing of state, restoring of state, transfer of state, checkpointing, manipulation of state information… For example, a logic chip etc. may detect an error, fatal error, unrecoverable error, imminent failure, error condition(s); [0161]: information may be sent between any system components (e.g. directly, indirectly, etc.) using any techniques. Examiner concludes that Smith teaches a test mode, analogous to an error detection, and that operations may be direct or indirect),
the plurality of memory units is configured to directly receive the memory command, the memory data and the memory address from an external source via the external port module ([0176]: one or more caches may be accessed directly by one or more CPUs; [0190]: In FIG. 3, in one embodiment, for example, the PHY layer may be coupled to one or more CPUs (e.g. system CPUs, CPUs on a die in the stacked memory package, external CPUs) without using the peripheral controller to detect failure bit addresses of each of the plurality of memory units ([0323]: one or more logic chips in a stacked memory package may be operable to map memory addresses…For example, in FIG. 8 the logic chip may contain and maintain (e.g. program, configure, create, update, modify, alter, etc.) an address mapping function 844…In FIG. 8 the address mapping function may contain one or more links (e.g. pointers, tables, indexes, combinations of these and/or other similar functions etc.) between one or more logical memory addresses (e.g. A1, A2, etc.) and the addresses, locations, status (e.g. bad, good, broken, replaced, to be replaced, testing, etc.). Examiner concludes that a circuit in the logic chip, analogous to a peripheral controller, may determine and store address locations of errors).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Smith to modified Zhou wherein in a case that a memory direct test mode is entered, the plurality of memory units is configured to directly receive the memory command, the memory data and the memory address from an external source via the external port module without using the peripheral controller to detect failure bit addresses of each of the plurality of memory units in order to improve execution speed and testing of stacked memory devices (Smith, [0208] & [0145]).
Regarding claim 8, Zhou, Morishita, Lynch, Shirakawa, and Smith together disclose the limitations of claim 7. Neither Zhou, Morishita, Lynch, nor Shirakawa discloses:
wherein the failure bit addresses are further written to the non-volatile memory circuit by the peripheral controller.
However, Smith teaches:
wherein the failure bit addresses are further written to the non-volatile memory circuit by the peripheral controller ([0325]: the memory system may use DRAM (e.g. in one or more stacked memory chips, etc.) or other volatile or nonvolatile storage (e.g. embedded DRAM, SRAM, NVRAM, NV logic, etc.) including storage on one or more logic chips etc. or combinations of storage elements, storage components, other memory, etc. to map one or more bad memory regions to one or more good memory regions. Examiner concludes that the addresses of the failure bits may be written to a non-volatile memory in a logic chip).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Smith to modified Zhou wherein the failure bit addresses are further written to the non-volatile memory circuit by the peripheral controller in order to improve execution speed and testing of stacked memory devices (Smith, [0208] & [0145]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou (CN 113934375 A), Morishita (US Pub. 20050156616 A1), Lynch (US Pub. 20040085818 A1), and Shirakawa (US Pub. 20160343445 A1) as applied to claim 1 above, and further in view of Chen et al. (US Pub. 20200357709 A1; “Chen”).
Regarding claim 10, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. Neither Zhou, Morishita, Lynch, nor Shirakawa discloses:
wherein the non-volatile memory circuit is a fuse memory circuit or a one-time programmable (OTP) memory circuit and is configured to store information for the operations of the plurality of memory units of the memory chip.
However, Chen teaches:
wherein the non-volatile memory circuit is a fuse memory circuit or a one-time programmable (OTP) memory circuit and is configured to store information for the operations of the plurality of memory units of the memory chip ([0033]: The information translated by the testing circuit 134 then may be stored in the failure storage space 142, which may be implemented as e-fuses, laser fuses or a non-volatile memory (NVM). Generally, the repair logic 140 may check repaired addresses stored in the failure storage space 142; [0047]: after the testing of the memory components through the testing circuit, replacement of a failed memory component of the memory components may be enabled with an information in relation to the testing result. As mentioned above, the repairing may be performed by the repairing circuit and the information may be repaired address stored in the failure storage space of the repairing circuit; [0008]: the control circuit may comprise a failure storage space storing an information in relation to perform repair process that a failed memory component is replaced. Examiner concludes that the memory within the control circuit is a fuse memory circuit and it stores information about the main memory).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chen to modified Zhou wherein the non-volatile memory circuit is a fuse memory circuit or a one-time programmable (OTP) memory circuit and is configured to store information for the operations of the plurality of memory units of memory chip in order to increase the bandwidth of the operation of the memory device by maximizing conductive contacts (Chen, [0007] & [0038]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou (CN 113934375 A), Morishita (US Pub. 20050156616 A1), Lynch (US Pub. 20040085818 A1), and Shirakawa (US Pub. 20160343445 A1) as applied to claim 1 above, and further in view of Chen (US Pub. 20200357709 A1) and Smith (US Pub. 20190205244 A1).
Regarding claim 11, Zhou, Morishita, Lynch, and Shirakawa together disclose the limitations of claim 1. Neither Zhou, Morishita, Lynch, nor Shirakawa discloses:
wherein the logic chip is bonded to the memory chip with a hybrid bond, and the external port module is coupled to the memory chip with through silicon vias (TSVs) and re-distribution layers (RDLs).
However, Chen teaches:
wherein the logic chip is bonded to the memory chip with a hybrid bond (in reference to Fig. 2, per [0037]: The transmission channels formed by the electrically connection between the conductive contacts 114, 126, may be formed with hybrid bonding technology. Bonding surfaces of the conductive contacts 114, 126, consisting of small metal pads and dielectric, are planarized and then bonded to form the physical joint between the first and second semiconductor portions 102, 104 for signal transmission therebetween; [0027]: the control circuit in the second semiconductor portion 104 is capable to access the memory components in the first semiconductor portion 102 for data storage), and the external port module ([0039]: The input/output channels may be conductive materials to transmit signals in and from or supply power to the semiconductor device 100, and therefore external signals may be input into the semiconductor device 1 and result calculated by the control circuit 132 may be output to an external device, such as a Printed Circuit Board (PCB). Examiner concludes that the external PCB is analogous to an external port module) is coupled to the memory chip with through silicon vias (TSVs) (according to another embodiment of Chen, per [0055]: The TSVs 428_1, 428_2 are used as input/output channels to transmit signals in and from or supply power to the semiconductor device 400)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Chen to modified Zhou wherein the logic chip is bonded to the memory chip with a hybrid bond, and the external port module is coupled to the memory chip with through silicon vias (TSVs) in order to increase the bandwidth of the operation of the memory device by maximizing conductive contacts (Chen, [0007] & [0038]).
Also, Smith teaches:
the external port module is coupled to the memory chip with re-distribution layers (RDLs) ([1177]: the memory system 18-200 may include one or more interconnection, coupling, connection, etc. structures etc. that may use, employ, implement, etc. one or more through-silicon via (TSV) structures, TSV arrays,…redistribution layers (RDLs),…multi-chip modules, 3D interconnect structures, face-to-face chip bonding, wafer-on-wafer structures; [0176]; [0190]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Smith to modified Zhou wherein the external port module is coupled to the memory chip with re-distribution layers (RDLs) in order to improve execution speed and testing of stacked memory devices (Smith, [0208] & [0145]).
Claims 13-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (CN 113934375 A), Morishita (US Pub. 20050156616 A1), Lynch (US Pub. 20040085818 A1), Shirakawa (US Pub. 20160343445 A1), Farmwald (US Pub. 20050141332 A1), and Smith (US Pub. 20190205244 A1).
Independent claim 13 contains limitations that are mostly the same as limitations from claims 1, 2, 5, and 6, and is thus rejected for the same reasons using Zhou, Morishita, Lynch, Shirakawa, and Farmwald.
Neither Zhou, Lynch, nor Shirakawa disclose:
wherein in the memory test mode, the plurality of memory units may be directly or indirectly tested through the external port module.
However, Morishita teaches:
wherein in the memory test mode, the plurality of memory units may be directly tested through the external port module (Fig. 12: tester 4; [0074])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Morishita to modified Zhou wherein in the memory test mode, the plurality of memory units may be directly tested through the external port module in order to reduce the parasitic capacitance between the logic chip and memory chip during testing of the face-to-face package (Morishita, [0083]).
Also, Smith teaches:
the plurality of memory units may be directly or indirectly tested through the external port module ([0451]: the test system may use one or more external CPUs (e.g. one or more CPUs coupled to one or more stacked memory chips, etc.) to perform part or portions of the test functions. Thus, in one embodiment, for example one or more test functions, operations, etc. may be shared between one or more CPUs and one or more test engines. Examiner notes that Smith teaches an external device performing the testing, but does not teach that the external device is a port module).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Smith to modified Zhou wherein the plurality of memory units may be directly or indirectly tested through the external port module in order to improve execution speed and testing of stacked memory devices (Smith, [0208] & [0145]).
Regarding claim 14, Zhou, Morishita, Lynch, Shirakawa, Farmwald, and Smith together disclose all the limitations of claim 13. Claim 14 recites substantially the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 16, Zhou, Morishita, Lynch, Shirakawa, Farmwald, and Smith together disclose all the limitations of claim 13. Claim 16 contains a first limitation that is mostly the same as the last limitation of claim 13, and is thus rejected for the same reasons. Claim 16 contains a second and a last limitation that are mostly the same as limitations of claim 5, and are thus rejected for the same reasons. Claim 16 contains a third limitation that is mostly the same as the ninth limitation of claim 1, and is thus rejected for the same reasons.
Regarding claim 17, Zhou, Morishita, Lynch, Shirakawa, Farmwald, and Smith together disclose all the limitations of claim 13. Claim 17 recites the same limitations as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 18, Zhou, Morishita, Lynch, Shirakawa, Farmwald, and Smith together disclose all the limitations of claim 13. Claim 18 recites mostly the same limitations as claim 7, and henceforth is rejected for the same reasons.
Regarding claim 19, Zhou, Morishita, Lynch, Shirakawa, Farmwald, and Smith together disclose all the limitations of claim 18. Claim 19 recites the same limitations as claim 8, and henceforth is rejected for the same reasons.
Regarding claim 20, Zhou, Morishita, Lynch, Shirakawa, Farmwald, and Smith together disclose all the limitations of claim 18. Claim 20 recites the same limitations as claim 12, and henceforth is rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824 /SULTANA BEGUM/Primary Examiner, Art Unit 2824
6/5/2026
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