Prosecution Insights
Last updated: October 23, 2026
Application No. 18/764,401

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Jul 05, 2024
Priority
Jul 07, 2023 — RE 10-2023-0088631
Examiner
PHAM, LONG
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1534 granted / 1675 resolved
+31.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
46 currently pending
Career history
1706
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
43.1%
+3.1% vs TC avg
§102
39.5%
-0.5% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1675 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-12, 19-10 in the reply filed on 8/2/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 7, and 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US pub 20240297120). With respect to claim 1, Chen et al. teach a semiconductor package comprising (see figs. 1-4D, particularly fig. 1B and associated text): a rewiring structure 114,108,106 including a rewiring pattern 108,106 and at least one insulating layer 114; a semiconductor device 110, 112 provided on the rewiring structure and electrically connected to the rewiring pattern; and a side surface protector 116 covering a first side surface (left) of the semiconductor device and extending to a side surface of the rewiring structure, wherein an upper surface of the semiconductor device, which is opposite to a lower surface of the semiconductor device facing the rewiring structure, and an upper surface of the side surface protector are at the same vertical level and are coplanar with each other, and the side surface protector extends from the insulating layer of the rewiring structure. With respect to claim 7, Chen et al. teach the insulating layer and the side surface protector are comprised of the same material (epoxy). See fig. 1B and associated text. With respect to claim 8, Chen et al. teach the insulating layer and the side surface protector are comprised of a photo imageable dielectric (PID) material (epoxy). See fig. 1B and associated text. Allowable Subject Matter Claims 19-20 are allowed. Claims 2-6, 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a stack of semiconductor device and rewiring structure, having a protective layer covering sides of the semiconductor device and rewiring structure, where upper surfaces of the device and the protective layer are co-planar as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 05, 2024
Application Filed
Oct 07, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12765420
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD
3y 9m to grant Granted Oct 13, 2026
Patent 12760145
POLYMER COMPOUND, AND ELECTROLUMINESCENT DEVICE MATERIAL AND ELECTROLUMINESCENT DEVICE INCLUDING POLYMER COMPOUND
3y 0m to grant Granted Oct 13, 2026
Patent 12765378
SEMICONDUCTOR APPARATUS
2y 4m to grant Granted Oct 13, 2026
Patent 12757762
WIRING BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 7m to grant Granted Oct 06, 2026
Patent 12751320
CHIP-ON-WAFER-ON-BOARD STRUCTURE USING SPACER DIE AND METHODS OF FORMING THE SAME
4y 3m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1675 resolved cases by this examiner. Grant probability derived from career allowance rate.

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