Prosecution Insights
Last updated: October 04, 2026
Application No. 18/764,470

Display Panel and Manufacturing Method Thereof

Non-Final OA §102
Filed
Jul 05, 2024
Priority
Jul 17, 2023 — CN 202310879072.7
Examiner
FERNANDES, ERROL V
Art Unit
Tech Center
Assignee
HKC Corporation Limited
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
701 granted / 821 resolved
+25.4% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
29 currently pending
Career history
830
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.3%
+22.3% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 4-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. US 2022/0093894 A1. Regarding claims 1, 4 and 6-8, Song discloses: A display panel (Fig. 4 in view of Fig. 2) comprising a plurality of pixel units arranged in an array, the pixel unit comprising a plurality of sub-pixels (100a), the display panel comprising an array substrate (100), and a pixel defining layer (200), a light-emitting functional layer (400) and an encapsulation layer (600) sequentially formed on the array substrate, in which the array substrate is formed with a plurality of first electrodes (302) arranged in an array, and the pixel defining layer comprises a plurality of pixel openings (region defined in 100a Pixel region) which expose at least part of the first electrode; the light-emitting functional layer comprises a light-emitting structure on the first electrode and a second electrode layer (500) on the light-emitting structure, wherein the display panel further comprises a boundary isolation layer (301) located on a side of the pixel defining layer away from the array substrate, the second electrode layer corresponding to two adjacent sub-pixels is disconnected at an edge of the boundary isolation layer, the boundary isolation layer comprises a conductive part (3011) and a shielding part (3012) located on a side of the conductive part away from the array substrate, and an orthographic projection of the shielding part on the array substrate covers an orthographic projection of the conductive part on the array substrate; and an end of the conductive part away from the shielding part is embedded in the pixel defining layer to prevent water and oxygen from infiltrating from the pixel defining layer into the light-emitting functional layer. (claim 4) Fig. 2; a groove (301a). (claims 6 and 7) para 0067. (claim 8) Fig. 2. Regarding claim 5, the examiner does not give patentable weight in regards to the claim limitation stating that “the conductive part is produced by printing” since such a limitation is taken to be a product-by-process limitation and is considered nonlimiting. A product by process claim is directed to the product per se, no matter how actually made. See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al, 218 USPQ 289, 292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned" from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not. Allowable Subject Matter Claims 2, 3 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 2 stating “wherein the conductive part comprises a tip part and a support part which are sequentially arranged along a light-emitting direction, the tip part is embedded in the pixel defining layer, and the support part is located between the tip part and the shielding part; the tip part is tapered away from the light-emitting direction, and the support part is tapered along the light-emitting direction”; and of claim 9 stating “wherein the encapsulation layer comprises a first inorganic layer, an organic layer and a second inorganic layer that are sequentially arranged in a direction away from the array substrate, in which the first inorganic layer and the second inorganic layer cover the light-emitting functional layer and the boundary isolation layer, and the organic layer has high elasticity and is sandwiched between the first inorganic layer and the second inorganic layer”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Claims 10-14 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations of claim 10 stating “forming a patterned pixel defining layer on the array substrate, wherein the pixel defining layer comprises a plurality of pixel openings and a plurality of grooves, and the pixel opening exposes at least part of the first electrode; printing a whole conductive layer on the pixel defining layer, wherein the conductive layer covers a plurality of the pixel openings and a plurality of the grooves; forming a whole shielding layer on the conductive layer; patterning the shielding layer and the conductive layer by photoetching to form a boundary isolation layer, wherein the boundary isolation layer comprises a conductive part and a shielding part located on a side of the conductive part away from the array substrate, an orthographic projection of the shielding part on the array substrate covers an orthographic projection of the conductive part on the array substrate, and an end of the conductive part away from the shielding part is embedded in the groove of the pixel defining layer”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Jul 05, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.8%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

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