DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Election/Restrictions
Applicant’s election without traverse of Invention I, drawn to claims 1-9 and 20, in the reply filed on 9/17/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 8, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (Pub. No.: US 20220416197 A1).
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Image A: closeup of Chen Fig. 4, showcasing partition wall opening, inner surfaces, and end portion.
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Image B: closeup of Chen Fig. 4, showcasing width consistency.
With regards to claim 1, Chen teaches a display panel comprising: a base layer (see Chen Fig. 4, substrate 1; Chen [0030]); a pixel defining film (see Chen Fig. 4, pixel definition layer 2; Chen [0030]) disposed on the base layer (see Chen Fig. 4), wherein a light emitting opening (see Chen Fig. 4, pixel openings 21; Chen [0035]) is defined in the pixel defining film (see Chen Fig. 4); a partition wall (see Chen Fig. 4, cathode isolation structure 3; Chen [0030]) including a first partition wall layer (see Chen Fig. 4, third isolation sub-layer 6; Chen [0039]) disposed on the pixel defining film (see Chen Fig. 4) and a second partition wall layer (see Chen Fig. 4, first isolation sub-layer 4; Chen [0031]) disposed on the first partition wall layer (see Chen Fig. 4), wherein a partition wall opening (see Image A) is defined in the partition wall to overlap the light emitting opening (see Image A); and a light emitting element (see Chen Fig. 4, anode 7, light-emitting function layer 8, and cathode 9; Chen [0035]&[0034]) including an anode (see Chen Fig. 4, anode 7; Chen [0035]), an intermediate layer (see Chen Fig. 4, light-emitting function layer 8; Chen [0035]), and a cathode (see Chen Fig. 4, cathode 9; Chen [0034]) in contact with the partition wall (see Chen Fig. 4), wherein at least a portion of the light emitting element is disposed inside the partition wall opening (see Image A), wherein a first inner surface (see Image A) of the first partition wall layer and a second inner surface (see Image A) of the second partition wall layer are aligned with each other (see Image A and see Chen [0044]: “Or optionally, as shown in FIG. 4, the orthographic projection of the third isolation sub-layer 6 on the substrate 1 may coincide with the orthographic projection of the first isolation sub-layer 4 on the substrate 1, that is, the cross section of the third isolation sub-layer 6 is larger than the cross section of the second isolation sub-layer 5 and equal to the cross section of the first isolation sub-layer 4.”).
With regards to claim 2, Chen teaches the display panel of claim 1, wherein the second partition wall layer (see Chen Fig. 4, first isolation sub-layer 4) includes an inorganic material (see Chen [0048]: “Optionally, in the display panel provided by an embodiment of the disclosure, the material of the first isolation sub-layer 4 and the material of the third isolation sub-layer 6 are generally inorganic materials,”).
With regards to claim 4, Chen teaches the display panel of claim 1, further comprising: a plurality of light emitting areas (see Chen [0035]: “Optionally, in the above-mentioned display panel provided by an embodiment of the disclosure, as shown in FIG. 1, the pixel definition layer 2 may include a plurality of pixel openings 21.”) from which lights provided from the light emitting element (see Chen Fig. 4, anode 7, light-emitting function layer 8, and cathode 9) are emitted (the light-emitting function layer 8 is in the pixel opening 21 and the light-emitting function layer 8 emits light, so due to the light-emitting function layer 8’s positioning, light is emitted from the plurality of pixel openings 21.), wherein the cathode (see Chen Fig. 4, cathode 9) is disconnected by the partition wall (see Chen Fig. 4, cathode isolation structure 3) to correspond to the plurality of light emitting areas ([0033] After the cathode of the entire surface is formed, the cathode isolation structure 3 provided by an embodiment of the disclosure can effectively isolate the cathode to form a desired cathode pattern.).
With regards to claim 8, Chen teaches the display panel of claim 1, wherein the cathode (see Chen Fig. 4, cathode 9) extends along the first inner surface (see Image A) of the first partition wall layer (see Chen Fig. 4, third isolation sub-layer 6), and an end portion (see Image A) of the cathode is in contact with the first partition wall layer (see Image A).
With regards to claim 9, Chen teaches the display panel of claim 1, wherein a width (see Image B) of the partition wall opening (see Image A) is constant (because third isolation sub-layer 6 and first isolation sub-layer 4 are equal in cross-sections (see Chen [0044]), the width between the two partition walls for those two layers would be constant.) along the first partition wall layer (see Chen Fig. 4, third isolation sub-layer 6) and the second partition wall layer (see Chen Fig. 4, first isolation sub-layer 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Shoda et al. (Patent. No.: US 7977866 B2), hereinafter as Shoda .
With regards to claim 3, Chen teaches the display panel of claim 1.
Chen does not teach that the second partition wall layer includes at least one selected from SiON and SiNx.
Shoda teaches a partition wall (see Shoda Fig. 3, partition wall 3 and covering a partition wall 4; Shoda col. 4, lns. 19-25) including a first partition wall layer (see Shoda Fig. 3, partition wall 3) and a second partition wall layer (see Shoda Fig. 3, covering a partition wall 4), where the second partition wall layer includes at least one selected from SiON and SiNx (see Shoda col. 6, lns. 22-26: “Inorganic insulating bodies such as oxide, nitride and fluoride such as SiO2, Sc2O3, TiO2, V2O5, Y2O3, ZrO2, Nb2O5, SiN, Si2N3, SiN4, SiF and MoO2 can be preferably used for a material of an insulating layer for covering a partition wall.”, where one would choose either SiN or SiN4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the material for the second partition wall layer of Chen with the material taught by Choi in order to utilize the excellent insulative and thermal resistant properties of silicon nitride.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Choi et al. (Pub. No.: US 20220130940 A1), hereinafter as Choi.
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Image C: closeup of Choi Fig. 10F, showcasing partition wall opening and side surface.
With regards to claim 5, Chen teaches the display panel of claim 1.
Chen does not teach a lower encapsulation inorganic pattern covering the light emitting element, wherein the lower encapsulation inorganic pattern is disposed inside the partition wall opening.
Choi teaches a lower encapsulation inorganic pattern (see Choi Fig. 10F, third insulating film 106; Choi [0107]) covering a light emitting element (see Choi Fig. 10F, anode electrode AE, second light emitting layer EL2, and second cathode electrode CE2; Choi [0057]), wherein the lower encapsulation inorganic pattern is disposed inside a partition wall opening (see Image C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a lower encapsulation inorganic pattern taught by Choi to the device of Chen in order to conform to the upper surfaces of the light emitting element and protect exposed parts of the light emitting element.
With regards to claim 6, Chen and Choi teach the display panel of claim 5, wherein a side surface (see Image C) of the lower encapsulation inorganic pattern (see Choi Fig. 10F, third insulating film 106) is in contact (due to the way third insulating film 106 is formed, it would be reasonable to assume it would contact the second inner surface.) with the second inner surface (see Image A) of the second partition wall layer (see Chen Fig. 4, first isolation sub-layer 4).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Choi, in view of Yanagisawa (Pub. No.: US 20250040373 A1).
With regards to claim 7, Chen and Choi teach the display panel of claim 5,
Chen and Choi do not teach an encapsulation organic film disposed on the lower encapsulation inorganic pattern, wherein the encapsulation organic film covers an upper surface of the second partition wall layer and an upper surface of the lower encapsulation inorganic pattern.
Yanagisawa teaches an encapsulation organic film (see Yanagisawa Fig. 10, resin layer 15; Yanagisawa [0095]) disposed on a lower encapsulation inorganic pattern (see Yanagisawa Fig. 10, sealing layer SE1; Yanagisawa [0083]; where the sealing layer SE1 is made of inorganic material (see Yanagisawa [0096])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add an encapsulation organic film taught by Yanagisawa to the combined device of Chen and Choi in order to cover the partition wall opening and prevent unwanted particulates from entering the opening.
Together, Chen, Choi, and Yanagisawa teach that the encapsulation organic film (see Yanagisawa Fig. 10, resin layer 15) covers (because it’s deposited on top of everything and is not etched away) an upper surface of the second partition wall layer (see Chen Fig. 4, first isolation sub-layer 4) and an upper surface of the lower encapsulation inorganic pattern (see Choi Fig. 10F, third insulating film 106).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nishioka et al. (Pub. No.: US 20190363139 A1), hereinafter as Nishioka, in view of Chen (Pub. No.: US 20220416197 A1), in further view of Choi et al. (Pub. No.: US 20220130940 A1), hereinafter as Choi.
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Image D: closeup of Nishioka Fig. 2, showcasing openings.
With regards to claim 20, Nishioka teaches a display panel comprising: a base layer (see Nishioka Fig. 2, substrate 1; Nishioka [0032]); a pixel defining film (see Nishioka Fig. 2, first bank 21; Nishioka [0038]) disposed on the base layer (see Nishioka Fig. 2), wherein a light emitting opening (see Image D) is defined in the pixel defining film (see Image D); a partition wall (see Nishioka Fig. 2, second banks 22; Nishioka [0038]) including a first partition wall layer (see Nishioka Fig. 2, second banks 22) disposed on the pixel defining film (see Nishioka Fig. 2) , wherein a partition wall opening (see Image D) is defined in the partition wall to overlap the light emitting opening (see Image D); a light emitting element (see Nishioka Fig. 2, organic EL elements 10; Nishioka [0033]) including an anode (see Nishioka Fig. 2, anode 11; Nishioka [0036]), an intermediate layer (see Nishioka Fig. 2, organic EL layer 12; Nishioka [0036]), and a cathode (see Nishioka Fig. 2, cathode 13; Nishioka [0036]) in contact with the partition wall (see Nishioka Fig. 2), wherein at least a portion of the light emitting element is disposed inside the partition wall opening (see Image D).
Nishioka does not teach a second partition wall layer disposed on the first partition wall layer.
Chen teaches a partition wall (see Chen Fig. 4, cathode isolation structure 3; Chen [0030]) including a first partition wall layer (see Chen Fig. 4, third isolation sub-layer 6; Chen [0039]) disposed on a pixel defining film (see Chen Fig. 4, pixel definition layer 2; Chen [0030]) and a second partition wall layer (see Chen Fig. 4, first isolation sub-layer 4; Chen [0031]) disposed on the first partition wall layer (see Chen Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a second partition wall layer taught by Chen to the device of Nishioka in order to further and more effectively separate light emitting elements from each other.
Nishioka and Chen do not teach a lower encapsulation inorganic pattern covering the light emitting element and disposed in the partition wall opening, wherein the lower encapsulation inorganic pattern does not overlap the partition wall in a thickness direction of the base layer.
Choi teaches a lower encapsulation inorganic pattern (see Choi Fig. 10F, third insulating film 106; Choi [0107]) covering a light emitting element (see Choi Fig. 10F, anode electrode AE, second light emitting layer EL2, and second cathode electrode CE2; Choi [0057]) and disposed in a partition wall opening (see Image A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a lower encapsulation in organic pattern taught by Choi to the combined device of Nishioka and Chen in order to conform to the upper surfaces of the light emitting element and protect exposed parts of the light emitting element.
Together, Nishioka, Chen, and Choi teach that the lower encapsulation inorganic pattern (see Choi Fig. 10F, third insulating film 106) does not overlap the partition wall in a thickness direction (because the lower encapsulation inorganic pattern does not overlap the top of Choi’s partition 105 and because the partition wall of Nishioka is rectangular, when the lower encapsulation inorganic pattern is disposed it would not overlap the partition wall in the thickness direction.) of the base layer (see Nishioka Fig. 2, substrate 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Fri, 8am-4pm ET.
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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