DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 17/661,491, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
Claim 1 recites the limitation “load address prediction circuitry” in line 2. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0058]) only appears to provide support for load address prediction “table” circuitry. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] load address prediction circuitry being implemented as a table, and does not appear to contemplate [the genus of] load address prediction circuitry that is not necessarily implemented as a table. Note that, for analogous rationale, the disclosure of the prior-filed application does not appear to provide support for dependent claims 2-11.
Claim 1 recites the limitation “load value prediction circuitry” in line 4. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0059]) only appears to provide support for load value prediction “table” circuitry. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] load value prediction circuitry being implemented as a table, and does not appear to contemplate [the genus of] load value prediction circuitry that is not necessarily implemented as a table. Note that, for analogous rationale, the disclosure of the prior-filed application does not appear to provide support for dependent claims 2-11.
Claim 1 recites the limitation “training circuitry that includes multiple entries, including: a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct” in lines 6-12. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0005], [0017], [0025], [0060], FIG. 2) only appears to provide support for the disclosed embodiments in the context of shared training circuitry wherein an entry is shared for load value prediction and load address prediction. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] shared training circuitry wherein an entry is shared for load value prediction and load address prediction, and does not appear to contemplate [the genus of] training circuitry that is not necessarily implemented via an entry that is shared for load value prediction and load address prediction. Note that, for analogous rationale, the disclosure of the prior-filed application does not appear to provide support for dependent claims 6-11. Note that the above rationale does not likewise apply to dependent claims 2-5, because claim 2 is directed to the aforementioned particular species, and claims 3-5 are dependent on claim 2.
Claim 3 recites the limitation “use the first field to store auxiliary address information for entries that are being trained for load address prediction” in line 4. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0028], [0030], [0031], [0063]) only appears to provide support for a predicted address stride in particular, rather than auxiliary address information in general. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] a predicted address stride, and does not appear to contemplate [the genus of] auxiliary address information that is not necessarily a predicted address stride. Note that while the above rationale does not likewise apply to dependent claim 4 (because claim 4 is directed to the aforementioned particular species), the disclosure of the prior-filed application does not appear to provide support for dependent claim 4 for another reason; see the subsequent paragraph.
Claim 4 recites the limitation “the auxiliary address information includes a predicted address stride” in lines 1-2. (Also note that claim 3 recites the limitation “use the first field to store auxiliary address information for entries that are being trained for load address prediction” in lines 4-5.) However, the disclosure of the prior-filed application does not appear to provide support for the aforementioned limitation of claim 4. For example, while the disclosure of the prior-filed application (e.g., paragraph [0028], [0030], [0031], [0063]) provides support for a predicted address stride, the disclosure of the prior-filed application (e.g., paragraph [0028], [0030], [0031], [0063]) does not appear to provide support for using the first field to store both a predicted address stride and a second entity of auxiliary address information for entries that are being trained for load address prediction, which is a scenario encompassed by the claim language in view of the open-ended “includes” language.
Claim 12 recites the limitation “storing, by the computer system in one or more training tables: a first entry configured with first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry with first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct” in lines 6-11. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0005], [0017], [0025], [0060], FIG. 2) only appears to provide support for the disclosed embodiments in the context of shared training circuitry wherein an entry is shared for load value prediction and load address prediction. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] shared training circuitry wherein an entry is shared for load value prediction and load address prediction, and does not appear to contemplate [the genus of] training circuitry that is not necessarily implemented via an entry that is shared for load value prediction and load address prediction. Note that, for analogous rationale, the disclosure of the prior-filed application does not appear to provide support for dependent claims 17-19. Note that the above rationale does not likewise apply to dependent claims 13-16, because claim 13 is directed to the aforementioned particular species, and claims 14-16 are dependent on claim 13.
Claim 12 recites the limitation “storing, by the computing system in one or more training tables: a first entry …” in lines 6-11. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, while the disclosure of the prior-filed application (e.g., paragraph [0020], [0028]) provides support for a training table, the disclosure of the prior-filed application (e.g., paragraph [0020], [0028]) does not appear to provide support for the aforementioned storing being in more than one training table, which is a scenario encompassed by the claim language in view of the “or more” language. Note that “the one or more training tables” is further recited in claim 17, lines 1-2. Note that, for analogous rationale, the disclosure of the prior-filed application does not appear to provide support for dependent claims 13-19.
Claim 14 recites the limitation “using, by the computer system, the first field to store auxiliary address information for entries that are being trained for load address prediction” in lines 4-5. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0028], [0030], [0031], [0063]) only appears to provide support for a predicted address stride in particular, rather than auxiliary address information in general. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] a predicted address stride, and does not appear to contemplate [the genus of] auxiliary address information that is not necessarily a predicted address stride. Note that while the above rationale does not likewise apply to dependent claim 15 (because claim 15 is directed to the aforementioned particular species), the disclosure of the prior-filed application does not appear to provide support for dependent claim 15 for another reason; see the subsequent paragraph.
Claim 15 recites the limitation “the auxiliary address information includes a predicted address stride” in lines 1-2. (Also note that claim 14 recites the limitation “using, by the computing system, the first field to store auxiliary address information for entries that are being trained for load address prediction” in lines 4-5.) However, the disclosure of the prior-filed application does not appear to provide support for the aforementioned limitation of claim 15. For example, while the disclosure of the prior-filed application (e.g., paragraph [0028], [0030], [0031], [0063]) provides support for a predicted address stride, the disclosure of the prior-filed application (e.g., paragraph [0028], [0030], [0031], [0063]) does not appear to provide support for using the first field to store both a predicted address stride and a second entity of auxiliary address information for entries that are being trained for load address prediction, which is a scenario encompassed by the claim language in view of the open-ended “includes” language.
Claim 20 recites the limitation “load address prediction circuitry” in line 3. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0058]) only appears to provide support for load address prediction “table” circuitry. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] load address prediction circuitry being implemented as a table, and does not appear to contemplate [the genus of] load address prediction circuitry that is not necessarily implemented as a table.
Claim 20 recites the limitation “load value prediction circuitry” in line 5. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0059]) only appears to provide support for load value prediction “table” circuitry. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] load value prediction circuitry being implemented as a table, and does not appear to contemplate [the genus of] load value prediction circuitry that is not necessarily implemented as a table.
Claim 20 recites the limitation “training circuitry that includes multiple entries, including: a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct” in lines 7-13. However, the disclosure of the prior-filed application does not appear to provide support for this limitation. For example, the disclosure of the prior-filed application (e.g., paragraph [0005], [0017], [0025], [0060], FIG. 2) only appears to provide support for the disclosed embodiments in the context of shared training circuitry wherein an entry is shared for load value prediction and load address prediction. Note that a claim may lack written description support when a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. In the instant case, the disclosure of the prior-filed application only appears to describe [the particular species of] shared training circuitry wherein an entry is shared for load value prediction and load address prediction, and does not appear to contemplate [the genus of] training circuitry that is not necessarily implemented via an entry that is shared for load value prediction and load address prediction.
Accordingly, claims 1-20 are not entitled to the benefit of the prior application.
Applicant states that this application is a continuation or divisional application of the prior-filed application. A continuation or divisional application cannot include new matter. Applicant is required to delete the benefit claim or change the relationship (continuation or divisional application) to continuation-in-part or amend the claims to remove the new matter because this application contains the following matter not disclosed in the prior-filed application: See above (regarding the claims), as well as the abstract (which contains subject matter analogous to subject matter noted with respect to the aforementioned claims).
Information Disclosure Statement
In the IDS dated July 5, 2024, U.S. Patent Application Publications 3-5 do not have a publication date.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
In the priority claim before paragraph [0001] of the specification, “continuation” should be “continuation of”.
In the priority claim before paragraph [0001] of the specification, the first instance of a quotation mark should precede “Shared” rather than “Learning”.
In the abstract, lines 7-8, it is unclear as to what is being conveyed by “note a given entry may be configured to load or value prediction at different times”. For example, it is unclear as to whether reference to load “address prediction” was intended; whether a given entry itself is configured to perform a load; and what it means for a given entry to be configured to “value prediction”).
Claim Objections
Claims 12-19 are objected to because of the following informalities. Appropriate correction is required.
In claim 12, line 9, an “or” should be inserted to precede the last recited element (i.e., a second entry) of the storing of claim 12, line 6.
Claims 13-19 are objected to for failing to alleviate the objection of claim 12 above.
In claim 18, line 4, “retrieve” should be “retrieving” for grammatical clarity.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12067398. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations of each of the aforementioned instant claims are taught by a corresponding claim of the ‘398 patent. As an exemplary case, see the table below, wherein standard-format limitations in the left column correlate to italicized limitations in the right column.
Claim 1 of Instant Application: 18764611
Claim 1 of U.S. Patent No. 12067398
1. An apparatus, comprising:
1. An apparatus, comprising:
load address prediction circuitry that includes multiple entries and is configured to store a predicted load address in a given entry;
hardware load address prediction table circuitry configured to store the following information for multiple entries: a load identifier and a predicted load address;
load value prediction circuitry that includes multiple entries and is configured to store a predicted load value in a given entry;
hardware load value prediction table circuitry configured to store the following information for multiple entries: a load identifier and a predicted load value;
training circuitry that includes multiple entries, including: a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct;
hardware learning table circuitry shared for load address prediction and load value prediction, wherein the hardware learning table circuitry is configured to store the following information for multiple entries: first predicted load address information, first predicted load value information, and a confidence indication of a level of confidence that at least one of the first predicted load address information and the first predicted load value information are correct;
control circuitry configured to, in response to an entry in the training circuitry reaching a threshold level of confidence, allocate a corresponding entry in either the load value prediction circuitry or the load address prediction circuitry; and
hardware control circuitry configured to, in response to an entry in the hardware learning table circuitry reaching a threshold level of confidence, allocate a corresponding entry in either the hardware load value prediction table circuitry or the hardware load address prediction table circuitry; and
pipeline circuitry configured to:
hardware pipeline circuitry configured to:
use a predicted load address from the load address prediction circuitry for a first load to retrieve data for the first load; and
use a predicted load address from the hardware load address prediction table circuitry for a first load to access a cache to retrieve data for the first load; and
use a predicted load value from the load value prediction circuitry for a second load as an input to one or more dependent instructions, prior to retrieving data for the second load.
use a predicted load value from the hardware load value prediction table circuitry for a second load as an input to one or more dependent instructions, prior to retrieving data for the second load from the cache.
All the limitations of instant claim 2 are taught by claim 6 of the ‘398 patent.
All the limitations of instant claim 3 are taught by claim 7 of the ‘398 patent.
All the limitations of instant claim 4 are taught by claim 7 of the ‘398 patent.
All the limitations of instant claim 5 are taught by claim 8 of the ‘398 patent.
All the limitations of instant claim 6 are taught by claim 1 of the ‘398 patent.
All the limitations of instant claim 7 are taught by claim 2 of the ‘398 patent.
All the limitations of instant claim 8 are taught by claim 3 of the ‘398 patent.
All the limitations of instant claim 9 are taught by claim 4 of the ‘398 patent.
All the limitations of instant claim 10 are taught by claim 5 of the ‘398 patent.
All the limitations of instant claim 11 are taught by claim 9 of the ‘398 patent.
All the limitations of instant claim 12 are taught by claim 10 of the ‘398 patent.
All the limitations of instant claim 13 are taught by claim 13 of the ‘398 patent.
All the limitations of instant claim 14 are taught by claim 7 of the ‘398 patent.
All the limitations of instant claim 15 are taught by claim 7 of the ‘398 patent.
All the limitations of instant claim 16 are taught by claim 14 of the ‘398 patent.
All the limitations of instant claim 17 are taught by claim 11 of the ‘398 patent.
All the limitations of instant claim 18 are taught by claim 11 of the ‘398 patent.
All the limitations of instant claim 19 are taught by claim 12 of the ‘398 patent.
All the limitations of instant claim 20 are taught by claim 11 of the ‘398 patent.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11, 13-16, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “training circuitry that includes multiple entries, including: a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct; control circuitry configured to, in response to an entry in the training circuitry reaching a threshold level of confidence, allocate a corresponding entry in either the load value prediction circuitry or the load address prediction circuitry; and pipeline circuitry” in lines 6-16. However, it is indefinite as to whether or not the recited training circuitry comprises the recited control circuitry and pipeline circuitry. For example, on one hand, the recited control circuitry and pipeline circuitry are at a same indent level as the recited training circuitry; on the other hand, there is no “and” language in claim 1, line 9, preceding “a second entry”. For the purposes of this office action, Examiner is taking the latter possibility to be the case.
Claims 2-11 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 2 recites the limitation “The apparatus of claim 1, wherein entries of the training circuitry are shared for load value prediction and load address prediction” in lines 1-2. Claim 1, upon which claim 2 is dependent, recites the limitation “training circuitry that includes multiple entries, including: a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct” in lines 6-12. However, the metes and bounds of the limitation of claim 2 in the context of claim 1 are indefinite, particularly what it means for an entry to be “shared” for load value prediction and load address prediction in the context of what is recited in claim 1, given that dependent claim 2 must include all the limitations of claim 1 to be a proper dependent claim. For example, it is indefinite as to whether claim 2 is implicitly conveying that an entry is configured to store a first field for first predicted load address information, a second field for a confidence indication of confidence that the first predicted load address information is correct, a third field for first predicted load value information, and fourth field for a confidence indication of confidence that the first predicted load value information is correct.
Claim 2 recites the limitation “the entry” in line 3. However, it is indefinite as to whether the antecedent basis for this limitation is “a given entry” in claim 1, line 3; “a given entry” in claim 1, line 5; “a first entry” in claim 1, line 7; “a second entry” in claim 1, line 10; “an entry” in claim 1, line 13; “a corresponding entry” in claim 1, line 14; or “a given entry” in claim 2, line 2. For the purposes of this office action, Examiner is taking the last possibility to be the case.
Claims 3-5 are rejected for failing to alleviate the rejections of claim 2 above.
Claim 6 recites the limitation “data” in line 2. However, it is indefinite as to whether this “data” is the same as, or different from, “data” as recited in claim 1, line 18. If the same, antecedent basis language should be used for clarity. For the purposes of this office action, Examiner is taking the two instances of data to be the same.
Claim 11 recites the limitation “processor circuitry that includes the load address prediction circuitry, load value prediction circuitry, training circuitry, control circuitry, and pipeline circuitry” in lines 2-3. However, it is indefinite as to whether the recited “the” language is intended to apply to a) just “load address prediction circuitry”, or b) all five of load address prediction circuitry, load value prediction circuitry, training circuitry, control circuitry, and pipeline circuitry. For the purposes of this office action, Examiner is taking the latter possibility to be the case.
Claim 11 recites the limitation “The apparatus of claim 1, wherein the apparatus is a computing device that further includes: processor circuitry that includes the load address prediction circuitry, load value prediction circuitry, training circuitry, control circuitry, and pipeline circuitry” in lines 1-4. Claim 1 previously recited the apparatus as comprising load address prediction circuitry, load value prediction circuitry, training circuitry, control circuitry, and pipeline circuitry. Therefore, it is indefinite as to what it means for the apparatus to “further” include an entity that includes that same load address prediction circuitry, load value prediction circuitry, training circuitry, control circuitry, and pipeline circuitry. For example, it is indefinite as to whether there are thus two instances of load address prediction circuitry, load value prediction circuitry, training circuitry, control circuitry, and pipeline circuitry.
Claim 13 recites the limitation “The method of claim 12, further comprising: sharing, by the computing system, entries of a training table of the one or more training tables for load value prediction and load address prediction” in lines 1-3. Claim 12, upon which claim 13 is dependent, recites the limitation “storing, by the computing system in one or more training tables: a first entry configured with first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry with first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct” in lines 6-11. However, the metes and bounds of the limitation of claim 13 in the context of claim 12 are indefinite, particularly what it means for an entry to be “shared” for load value prediction and load address prediction in the context of what is recited in claim 12, given that dependent claim 13 must include all the limitations of claim 12 to be a proper dependent claim. For example, it is indefinite as to whether claim 13 is implicitly conveying that an entry is configured to store a first field for first predicted load address information, a second field for a confidence indication of confidence that the first predicted load address information is correct, a third field for first predicted load value information, and fourth field for a confidence indication of confidence that the first predicted load value information is correct.
Claim 13 recites the limitation “the entry” in line 4. However, it is indefinite as to whether the antecedent basis for this limitation is “an entry” in claim 12, line 2; “an entry” in claim 12, line 4; “a first entry” in claim 12, line 7; “a second entry” in claim 12, line 10; “an entry” in claim 12, line 12; “a corresponding entry” in claim 12, line 13; or “a given entry” in claim 13, line 3. For the purposes of this office action, Examiner is taking the last possibility to be the case.
Claim 13 recites the limitation “the training table” in line 4. However, it is indefinite as to whether the antecedent basis for this limitation is “a training table” in claim 12, line 12, or “a training table” in claim 13, line 2. Note that this limitation is also recited in claim 14, line 2.
Claims 14-16 are rejected for failing to alleviate the rejections of claim 13 above.
Claim 20 recites the limitation “training circuitry that includes multiple entries, including: a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct; a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct; control circuitry configured to, in response to an entry in the training circuitry reaching a threshold level of confidence, allocate a corresponding entry in either the load value prediction circuitry or the load address prediction circuitry; and pipeline circuitry” in lines 7-17. However, it is indefinite as to whether or not the recited training circuitry comprises the recited control circuitry and pipeline circuitry. For example, on one hand, the recited control circuitry and pipeline circuitry are at a same indent level as the recited training circuitry; on the other hand, there is no “and” language in claim 20, line 10, preceding “a second entry”. For the purposes of this office action, Examiner is taking the latter possibility to be the case.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. While the claim(s) do recite circuitry, paragraphs [0086] and [00115] specify VHDL embodiments. For example, paragraph [0086] discloses “design information 1015 may specify the circuit elements”, and paragraph [00115] discloses “Thus, the microarchitectural definition is recognized by those of skill in the art as structure from which many physical implementations may be derived, all of which fall into the broader structure described by the microarchitectural definition. That is, a skilled artisan presented with the microarchitectural definition supplied in accordance with this disclosure may, without undue experimentation and with the application of ordinary skill, implement the structure by coding the description of the circuits/units/components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a fashion that may appear to be functional. But to those of skill in the art in this field, this HDL description is the manner that is used transform the structure of a circuit, unit, or component to the next level of implementational detail.” As such, Examiner recommends inserting the limitation “hardware” in an appropriate part of the claim and all relevant places in further dependent claims (e.g. replacing the limitation “control circuitry” with the limitation “hardware control circuitry”). Note that dependent claim 11 and independent claim 20 are not being rejected in view of their recitation of a display.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sato (A Simulation Study of Combining Load Value and Address Predictors) discloses “There are few studies investigating predictors that combine a load value predictor and a load address predictor…” (page 3, first indented paragraph). Sato discloses tables used for load value prediction (page 5, FIG. 2) and a table used for load address prediction (page 7, FIG. 4). Sato further discloses “a dynamic hybrid predictor consists of a load value predictor, a load address predictor, and a predictor selection counter. Whenever a load instruction is encountered both the value and the address predictors initiate prediction. The selection counter decides which predictor is used. When the counter value is larger than a threshold, the value predictor is selected. Otherwise, the address predictor is used” (page 8, section 3.3, first paragraph). Therefore, Sato is relevant to the claimed load address prediction table circuitry, load value prediction table circuitry, predicted load address information, predicted load value information, and confidence indication.
Sato (Reducing Miss Penalty of Load Value Prediction using Load Address Prediction) discloses “a combination of the load value predictor and a load address predictor. Address prediction enjoys better accuracy than value prediction, but does not result in as big a win when correct. Therefore, address prediction is proposed to be used in cases where value prediction is unable to predict a load. I call this predictor a cooperative predictor. Furthermore, I investigate to verify predicted values using the address predictor, thereby misprediction penalty can be further reduced. A predicted value is compared with the one which is obtained using the predicted address. I call this scheme speculative verification. With the help of the speculative verification, a recovery action caused by a misprediction is initiated earlier than the time when the misprediction is really detected” (page 2, first indented paragraph). Sato further discloses “To the best of our knowledge, predictors combining a load value predictor and a load address predictor have not been investigated. The predictor proposed by Gonzalez et al. [Gonzalez et al.,1997] predicts both load values and addresses, but the load values are obtained using the predicted load addresses. Thus, the load address predictor and the load value predictor do not work independently. On the other hand, our proposed load value predictor does not use the predicted address and hence works independently of the load address predictor. Furthermore, the verification of predicted values can be accelerated using the predicted address” (page 3, second indented paragraph). Therefore, Sato is relevant to the claimed load address prediction table circuitry, load value prediction table circuitry, predicted load address information, and predicted load value information.
Gonzalez (Speculative Execution via Address Prediction and Data Prefetching) discloses “in the case of load instructions, the address of the next execution is predicted and the value is brought from memory into a structure called Memory Prefetching Table (MPT) in order to be available for the next execution of the same load instruction. When a load arrives at the decode stage, its effective address is predicted and the entry obtain from the MPT is checked in order to know if the value has been prefetched. If the value is available, the load destination register is updated and all the subsequent dependent instruction will be allowed to be executed speculatively. Otherwise, the predicted address will be used to speculatively issue this load and the instructions dependent on it. Several cycles later, memory instructions will verify their prediction. If the prediction is correct and the load obtained the value at decode stage from the MPT, it will not require any further memory access. In the case of a misprediction, all the misspeculated instructions will be reexecuted” (page 196, right column, fourth paragraph). Gonzalez further discloses the memory prefetching table having an effective address field, stride field, stride history bits field used to assign confidence, value field that contains the value brought from data cache that will likely be the value requested by the next execution of the load instruction, and valid field (page 198, right column, last paragraph to page 199, left column, end of the aforementioned paragraph). Therefore, Gonzalez is relevant to the claimed address prediction, load value prediction, and confidence.
Reinman et al. (Predictive Techniques for Aggressive Load Speculation) discloses address predictions for loads in section 4, value prediction in section 5, and a Load-Spec-Chooser in section 7 wherein predictors report their confidence at predicting a particular load, and priority is given to value prediction before address prediction. Therefore, Reinman is relevant to the claimed load address prediction table circuitry, load value prediction table circuitry, predicted load address information, and predicted load value information, and confidence.
Orosa et al. (AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction) discloses “two tables that compose the AVPP predictor. The Address Table (AT) is indexed by the instruction address, and it returns the predicted address. The Value Table (VT) is indexed by the predicted address, and it returns the corresponding predicted value, which has to be prefetched in advance.” (See page 49:6, section 4.1, second paragraph.) Therefore, Orosa is relevant to the claimed load address prediction table circuitry, load value prediction table circuitry, predicted load address information, and predicted load value information.
Wang et al. (Highly Accurate Data Value Prediction using Hybrid Predictors) discloses a block diagram of a hybrid (2-level, stride) predictor (see page 288, Figure 6) and discloses “when a prediction is to be made for an instruction, the appropriate VHT entry is selected, and its Tag field checked as before. In parallel, the Value History Pattern and the State fields are read out for the 2-level predictor and the stride-based predictor. The 2-level predictor makes a prediction if the maximum count value in the selected PHT entry is greater than the specified threshold value. If the 2-level predictor makes a prediction, then that value is selected as the hybrid predictor’s prediction. If the 2-level predictor does not make a prediction, then the value predicted (if any) by the stride-based predictor is selected” (see page 288, section 5.2). Therefore, Wang is relevant to the claimed load value prediction.
Chou et al. (US 20210049015 A1) discloses a load prediction table entry (see FIG. 4) and load prediction learning table entry (see FIG. 4), which is relevant to the claimed load address prediction table circuitry and learning table circuitry.
Al Sheikh et al. (US 20200364055 A1) discloses load address prediction and load value prediction (see FIG. 1, [0025]-[0029]), which is relevant to the claimed load address prediction and load value prediction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEITH E VICARY/Primary Examiner, Art Unit 2182
Prosecution Insights