Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 12/23/2025 has been entered. Claims 1 and 8 have been amended. Claims 14-15 have been added. Claims 1 and 3-15 remain pending in the application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 and 3-7 are rejected under 35 U.S.C. 103 as unpatentable over Choi (US 11783617 B2) in view of AKIYAMA (US 20130075761 A1).
Regarding claim 1, Choi (e.g., Figs. 2-3 and 7-9; Fig. 7 is reproduced for reference) discloses a semiconductor device comprising a pixel comprising a first pixel circuit (pixel circuit PX1) and a second pixel circuit (pixel circuit PX2),
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wherein the first pixel circuit (pixel circuit PX1) comprises a first light-receiving device (light-receiving element PD1), a second light- receiving device (light-receiving element PD2), a first transistor (transistor T10), a second transistor (transistor T7), and a capacitor (capacitor C2),
wherein the second pixel circuit (pixel circuit PX2) comprises a first light-emitting device (light-emitting element OLED),
wherein one of a source and a drain of the first transistor (transistor T10) is electrically connected to a first electrode of the first light-receiving device (light-receiving element PD1),
wherein one of a source and a drain of the second transistor (transistor T7) is electrically connected to a first electrode of the second light-receiving device (light-receiving element PD2),
wherein the other of the source and the drain of the first transistor (transistor T10) is electrically connected to an electrode of the capacitor (capacitor C2), wherein the other of the source and the drain of the second transistor (transistor T7) is electrically connected to the electrode of the capacitor (capacitor C2).
Choi does not disclose wherein a conductive film comprises a region configured to be a second electrode of the first light-receiving device, a region configured to be a second electrode of the second light- receiving device, and a region configured to be a first electrode of the first light-emitting device. However, AKIYAMA (e.g., Figs. 3-12, 16-17, and 25-28, Fig. 3 and Fig. 26 are reproduced for reference) discloses a semiconductor device comprising a pixel comprising a first pixel circuit (pixel circuit PX1) and a second pixel circuit (pixel circuit PX2),
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wherein the first pixel circuit (pixel circuit PX1) comprises a first light-receiving device (light-receiving element PD1), a second light- receiving device (light-receiving element PD2), a first transistor (transistor 110-1), and a second transistor (transistor 110-2),
wherein the second pixel circuit (pixel circuit PX1) comprises a first light-emitting device (light-emitting element LED),
wherein one of a source and a drain of the first transistor (transistor 110-1) is electrically connected to a first electrode of the first light-receiving device (light-receiving element PD1),
wherein one of a source and a drain of the second transistor (transistor 110-2) is electrically connected to a first electrode of the second light-receiving device (light-receiving element PD2),
wherein the other of the source and the drain of the first transistor (transistor 110-1) is electrically connected to the other of the source and the drain of the second transistor (transistor 110-2), and
wherein a conductive film comprises a region configured to be a second electrode of the first light-receiving device, a region configured to be a second electrode of the second light- receiving device, and a region configured to be a first electrode of the first light-emitting device (e.g., Figs. 3, 6, 20-23, and 28, conductive layer comprising an electrode 301 of first light-receiving element PD1, an electrode 301 of second light-receiving element PD2, and an electrode 201 of light-emitting element LED).
Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from AKIYAMA to the semiconductor device of Choi. The combination/motivation would be to provide a light source-sensor integrated type photoelectric device and a manufacturing method. In addition, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the capacitor as taught from Choi to the photoelectric device of AKIYAMA to control the charging and discharging of the light-receiving elements and the differential signal generation (Choi, col. 7, lines 26-61 and col. 11, line 29-63).
Regarding claim 3, Choi in view of AKIYAMA discloses the semiconductor device according to claim 1. Choi (e.g., Fig. 7) discloses wherein the first light-emitting device (light-emitting element OLED) is configured to emit visible light (claims 1 and 8; visible light).
Regarding claim 4, Choi in view of AKIYAMA discloses the semiconductor device according to claim 1. AKIYAMA (e.g., Figs. 3-12, 16-17, and 25-28) discloses wherein the first light-emitting device is configured to emit infrared light ([0064] and [0082]).
Regarding claim 5, Choi in view of AKIYAMA discloses an electronic device comprising: the semiconductor device according to claim 1; AKIYAMA (e.g., Figs. 3-12, 16-17, and 25-28) discloses a second light-emitting device (light-emitting element LED2); and a housing (e.g., Fig. 2; housing), wherein the second light-emitting device is configured to emit infrared light ([0064] and [0082]), and wherein the second light-emitting device is configured to emit light to an outside through the semiconductor device (e.g., Fig. 2; housing).
Regarding claim 6, Choi in view of AKIYAMA discloses the semiconductor device according to claim 3, AKIYAMA discloses further comprising a layer (e.g., Figs. 3, 6, 20-23, and 28; base layer 100 or transistor TFT layer), wherein the first light-receiving device (light-receiving element PD1) and the first light-emitting device (light-emitting element LED1) are provided over the layer (base layer 100 or transistor TFT layer).
Regarding claim 7, Choi in view of AKIYAMA discloses the semiconductor device according to claim 6, AKIYAMA discloses wherein the layer (e.g., Figs. 3, 6, 20-23, and 28; transistor TFT layer) comprises the first transistor (transistor 110-1) and the second transistor (transistor 110-2).
5. Claims 8-13 are rejected under 35 U.S.C. 103 as unpatentable over Choi (US 11783617 B2) in view of Yamaguchi (US 20060244693 A1) and further in view of AKIYAMA (US 20130075761 A1).
Regarding claim 8, Choi (e.g., Figs. 2-3 and 7-9; Fig. 7 is reproduced for reference) discloses a semiconductor device comprising:
a pixel comprising a first pixel circuit (pixel circuit PX1) and a second pixel circuit (pixel circuit PX2),
wherein the first pixel circuit (pixel circuit PX1) comprises a first light-receiving device (light-receiving element PD1), a second light- receiving device (light-receiving element PD2), a first transistor (transistor T10), a second transistor (transistor T7), and a capacitor (capacitor C2),
wherein the second pixel circuit (pixel circuit PX2) comprises a first light-emitting device (light-emitting element OLED),
wherein one of a source and a drain of the first transistor (transistor T10) is electrically connected to a first electrode of the first light-receiving device (light-receiving element PD1),
wherein one of a source and a drain of the second transistor (transistor T7) is electrically connected to a first electrode of the second light-receiving device (light-receiving element PD2),
wherein the other of the source and the drain of the first transistor (transistor T10) is electrically connected to an electrode of the capacitor (capacitor C2),
wherein the other of the source and the drain of the second transistor (transistor T7) is electrically connected to the electrode of the capacitor (capacitor C2).
Choi does not disclose wherein the first light-receiving device is configured to sense visible light, and wherein the second light-receiving device is configured to sense infrared light. However, Yamaguchi (e.g., Figs. 1, 11-13, and 16) discloses a semiconductor device comprising a pixel comprising a first pixel circuit and a second pixel circuit, wherein the first pixel circuit comprises a first light-receiving device, a second light- receiving device, (Fig. 11; pixel circuit CR comprising a first light-receiving element 111A and a second light receiving element 111B, [0103]), wherein the second pixel circuit comprises a first light-emitting device (Fig. 16; pixel circuit CW comprising a light-emitting element EL),wherein the first light-receiving device is configured to sense visible light (Fig. 11 and claims 9-10 and [0103]), and wherein the second light-receiving device is configured to sense infrared light (Fig. 11 and claims 9-10 and [0103]). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from Yamaguchi to the electronic device of Choi. The combination/motivation would be to provide an electronic device including a visible light sensor and an infrared light sensor for biological image sensing and user identification.
Choi does not disclose wherein a conductive film comprises a region configured to be a second electrode of the first light-receiving device, a region configured to be a second electrode of the second light- receiving device, and a region configured to be a first electrode of the first light-emitting device. However, AKIYAMA (e.g., Figs. 3-12, 16-17, and 25-28) discloses a semiconductor device similar to that disclosed by Choi, wherein a conductive film comprises a region configured to be a second electrode of the first light-receiving device, a region configured to be a second electrode of the second light- receiving device, and a region configured to be a first electrode of the first light-emitting device (e.g., Figs. 3, 6, 20-23, and 28, conductive layer comprising an electrode 301 of first light-emitting element PD1, an electrode 301 of second light-emitting element PD2, and an electrode 201 of light-emitting element LED). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from AKIYAMA to the electronic device of Choi. The combination/motivation would be to provide a light source-sensor integrated type photoelectric device and a manufacturing method. In addition, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the capacitor as taught from Choi to the photoelectric device of AKIYAMA to control the charging and discharging of the light-receiving elements and the differential signal generation (Choi, col. 7, lines 26-61 and col. 11, line 29-63).
Regarding claim 9, Choi in view of Yamaguchi and further in view of AKIYAMA discloses the semiconductor device according to claim 8, Yamaguchi discloses wherein the first light-emitting device is configured to emit visible light (e.g., Fig. 16, light-emitting element ELr, ELg, or ELb emits red, green, or blue color light, respectively).
Regarding claim 10, Choi in view of Yamaguchi and further in view of AKIYAMA discloses the semiconductor device according to claim 8, Yamaguchi discloses wherein the first light-emitting device is configured to emit infrared light (e.g., Fig. 16, light-emitting element ELIR emits infrared light).
Regarding claim 11, Choi in view of Yamaguchi and further in view of AKIYAMA discloses the semiconductor device according to claim 8, Yamaguchi discloses an electronic device comprising: the semiconductor device according to claim 8; a second light-emitting device (e.g., Fig. 16, light-emitting element ELIR emits infrared light); and a housing (e.g., Figs. 15 and 18-21), wherein the second light-emitting device is configured to emit infrared light (e.g., Fig. 16, light-emitting element ELIR emits infrared light), and wherein the second light-emitting device is configured to emit light to an outside through the semiconductor device (e.g., Figs. 15 and 18-21).
Regarding claim 12, Choi in view of Yamaguchi and further in view of AKIYAMA discloses the semiconductor device according to claim 8, Yamaguchi (e.g., Figs. 14-20) discloses further comprising a layer (base layer 602), wherein the first light-receiving device (light-receiving element 110) and the first light-emitting device (light-remitting element EL) are provided over the layer (base layer 602). AKIYAMA also discloses further comprising a layer (e.g., Figs. 3, 6, 20-23, and 28; base layer 100 or transistor TFT layer), wherein the first light-receiving device (light-receiving element PD1) and the first light-emitting device (light-emitting element LED1) are provided over the layer (base layer 100 or transistor TFT layer).
Regarding claim 13, Choi in view of Yamaguchi and further in view of AKIYAMA discloses the semiconductor device according to claim 8, AKIYAMA discloses wherein the layer (e.g., Figs. 3, 6, 20-23, and 28; transistor TFT layer) comprises the first transistor (transistor 110-1) and the second transistor (transistor 110-2).
6. Claim 14 is rejected under 35 U.S.C. 103 as unpatentable over Choi (US 11783617 B2) in view of AKIYAMA (US 20130075761 A1) and further in view of KIMURA (US 20170125466 A1).
Regarding claim 14, Choi in view of AKIYAMA discloses the semiconductor device according to claim 1, but does not disclose wherein an area of a light- receiving region of the first light-receiving device is smaller than an area of a light-receiving region of the second light-receiving device. However, KIMURA (e.g., Figs. 2-3, 6, and 19-21) discloses a semiconductor device similar to that disclosed by Choi and AKIYAMA, wherein an area of a light- receiving region of the first light-receiving device is smaller than an area of a light-receiving region of the second light-receiving device (e.g., Figs. 2-3 and 6; light-receiving element PD2 has a smaller area that light-receiving element PD1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIMURA to the photoelectric device of Choi in view of AKIYAMA to improve the performance of the photo sensing.
7. Claim 15 is rejected under 35 U.S.C. 103 as unpatentable over Choi (US 11783617 B2) in view of Yamaguchi (US 20060244693 A1) and AKIYAMA (US 20130075761 A1) and further in view of KIMURA (US 20170125466 A1).
Regarding claim 15, Choi in view of Yamaguchi and further in view of AKIYAMA discloses the semiconductor device according to claim 1, but does not disclose wherein an area of a light- receiving region of the first light-receiving device is smaller than an area of a light-receiving region of the second light-receiving device. However, KIMURA (e.g., Figs. 2-3, 6, and 19-21) discloses a semiconductor device similar to that disclosed by Choi, Yamaguchi, and AKIYAMA, wherein an area of a light- receiving region of the first light-receiving device is smaller than an area of a light-receiving region of the second light-receiving device (e.g., Figs. 2-3 and 6; light-receiving element PD2 has a smaller area that light-receiving element PD1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIMURA to the photoelectric device of Choi in view of Yamaguchi and AKIYAMA to improve the performance of the photo sensing.
Response to Arguments
9. Regarding claims 1 and 8, applicant’s arguments have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In view of amendments and the new claims, the reference Choi (US 11783617 B2) has been used for new ground rejection. Regarding new claims 14 and 15, the reference KIMURA (US 20170125466 A1) has been used for new ground rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623