Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 03/19/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/21/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over combination of Oreggia et al. (USPGPUB No. 2023/0350840 A1, hereinafter referred to as Oreggia) in view of Chen et al. (USPGPUB No. 20200103705 A1, hereinafter referred to as Chen) and further in view of De Renzis (USPGPUB No. 2018/0259941 A1, hereinafter referred to as Renzis) in view of Snyder et al. (USPGPUB No. 2016/0183351 A1, hereinafter referred to as Snyder) and further in view of Kessler et al. (USPGPUB No. 20170220502 A1, hereinafter referred to as Kessler).
Referring to claim 1, Oreggia discloses a method of synchronization signal transmission {“data signal, and a synchronization signal,”, see Fig. [0005], last sentence} for a serial communication system {“convert the three-pin signal into the Isolated [serial peripheral interface] SPI signal”, [0005] last sentence} having a master device {“When the BMIC 100 works in master mode”, see Figs. 1 and 2, [0028], 1st sentence} and a plurality of slave devices coupled in series {“The slave BMICs 213S are connected in a daisy chain configuration”, see Figs. 1 and 2, as claimed to the master device, [0038], 2nd sentence}, the method comprising:
a) controlling the plurality of slave devices {“ISOLP_SDI and ISOLM_NCS of each slave BMIC 213S form a first Isolated SPI interface”, see Fig. 2 [0038]}, in order to form a linked pathway when a synchronization signal {“synchronization signal labeled as SCK in FIG. 4A”, [0047], last sentence}, needs to be transmitted {“standard SPI signal (which may include four signal lines such as SDI, NCS, SDO, and SCK) is applied at the I/O pins labeled as [linked pathway] ISOLP_SDI”, see Figs. 1 and 4a [0028], 2nd sentence};
and b) transmitting the synchronization signal to the linked pathway {“synchronization signal labeled as SCK in FIG. 4A”, [0047], last sentence}, such that each of the plurality of slave devices receives the synchronization signal at the same time {“where each bit frame has a [same duration] duration (referred to as a bit frame duration) of T” per slave device (see Fig. 3, [0034], 3rd sentence}.
Oreggia does not appear to explicitly disclose a) controlling the plurality of slave devices;
However, Chen discloses a) controlling the plurality of slave devices {“duty cycle of the PWM signals can be modulated to control the period of time during which each LED string is turned on”, see Fig. 4b, [0075]}.
Oreggia and Chen are analogous because they are from the same field of endeavor, master/slave device communications.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Oreggia and Chen before him or her, to modify Oreggia’s “BMIC 100” (see Figs. 1 and 2) in view of Chen’s “two backlight driver integrated circuit chips 64-1 and 64-2” and corresponding “various LED strings (see Fig. 4b, [0073], [0074]).
The suggestion/motivation for doing so would have been to implement/provide a mechanism for detecting the number of faulty LED strings within the backlight unit (Chen [0099], last sentence) such that an in-rush controller might also be formed at the output of boost converter 70 or at any suitable intermediate location within boost converter 70 to help reduce the risk of damage caused by inadvertent short faults (see Figs. 11a and 11b, Chen [0163]).
Therefore, it would have been obvious to combine Chen with Oreggia to obtain the invention as specified in the instant claim(s).
However, neither Oreggia or Chen appears to explicitly disclose a) controlling the plurality of slave devices to be in a through state;
However, De Renzis discloses a) controlling the plurality of slave devices {“ Each of the two or more slave units 6 is [controlled] programmed to transmit”, see Fig. 6, [0133]} to be in a through state {“synchronization signal that is received almost simultaneously by all the slave units” ([0061], 2nd sentence) for influencing through state “A corresponding timing information detected” ([0142])}.
Oreggia/Chen and De Renzis are analogous because they are from the same field of endeavor, master/slave device communications.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Oreggia/Chen and De Renzis before him or her, to modify Oreggia/Chen’s system incorporating De Renzis’ “slave units 6” (see Fig. 6) and respective “high precision clock” ([0142]) to achieve the claimed synchronization/through state.
The suggestion/motivation for doing so would have been to implement a diagnostic block to read voltage and current or other quantities representing an electricity consumption by the system, without causing alterations in the electrical power supply of the electronic components of the master unit (De Renzis [0078]) which in turn makes the data processing and transmission system particularly reliable, allowing the energy consumption to be monitored and identifying any faults, with the possibility of generating warning or fault signals and preventing these situations (De Renzis [0079]).
Therefore, it would have been obvious to combine De Renzis with Oreggia/Chen to obtain the invention as specified in the instant claim(s).
However, neither one of the group Oreggia, Chen, De Renzis appears to explicitly disclose wherein N is an integer that is at least two; in order to form a linked pathway before a synchronization signal needs to be transmitted, wherein the linked pathway is formed from an output port of the master device to an output port of an Nth slave device through the N slave devices; the N slave devices to be in a through state;
However, Snyder discloses wherein N is an integer that is at least two {“using two stacked physical channels”, see Fig. 1 [0060]); in order to form a linked pathway {“DMX for controlling power sequencing and combining power”, see Fig. 1, Table 2 after [0092]) before a synchronization signal needs to be transmitted {“ create [synchronization signals] time bins for N groups of LEDs”, see Fig. 1 [0044]), wherein the linked pathway is formed from an output port of the master device {“DMX channels for a light, or string of lights, can be assigned on-the-fly”, see Fig. 1 [0149]; “single DMX512 controller—which is the master of the network”, [0106], 2nd sentence) to an output port of an Nth slave device {“more lights can operate on the same output port.”, Table 2 after [0092]) through the N slave devices {“employed as the controller for a network of slave devices such as dimmer”, see Fig. 1 [0106], last sentence); the N slave devices to be in a through state {“Time Division Multiplexing scheme to [through state] sequence PWM duty cycle start times to be off-set”, see Fig. 1, Table 2, after [0092]).
Oreggia/Chen/De Renzis and Snyder are analogous because they are from the same field of endeavor, master/slave device communications.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Oreggia/Chen/De Renzis and Snyder before him or her, to modify Oreggia/Chen/De Renzis’ system incorporating Snyder’s “controller 132” and corresponding “DMX channel” (see Figs. 1 and 2).
The suggestion/motivation for doing so would have been to implement a Power-over-Ethernet LED Lighting system, method, and apparatus for powering intelligent lighting networks that is cost effective and energy efficient. The power for such an intelligent lighting network would be supplied by Power-over-Ethernet switches and/or Mid-Spans, which are conditioned by a powered device to distribute power tuned specifically for each, at least one LED fixture. (Snyder [0008]).
Therefore, it would have been obvious to combine Snyder with Oreggia/Chen/De Renzis to obtain the invention as specified in the instant claim(s).
However neither one of the group consisting of Oreggia, Chen, De Renzis, and Snyder appears to explicitly disclose transmitting a specific instruction indicating that a synchronization signal needs to be transmitted by the master device;
b) receiving the specific instruction by each of the N slave devices;
c) controlling coupling the input and output of each of the N slave devices when receiving the specific instruction, such that the N slave devices are controlled to be in a through state;
However, Kessler discloses disclose transmitting a specific instruction {“synchronization control frame 180”, see Fig. 3, [0067], 1st sentence indicating that a synchronization signal {“synchronization control frame 180 may be used for [indicating] data clock recovery and [synchronization signal] PLL synchronization,”, see Fig. 3, [0067], 2nd sentence} needs to be transmitted by the master device {“the master node 102 transmits a synchronization control frame (SCF)”, see Fig. 8 [0114], 1st sentence};
b) receiving the specific instruction {“[receiving and] forwards the [specific instruction] synchronization control frame”, see Fig. 8, [0114], 2nd sentence} by each of the N slave devices {“Each successive slave node 104”, see Fig. 8 [0114], 2nd sentence};
c) controlling coupling the input and output {“optionally inserts data from one or more microphones coupled [input or output]”, see Fig. 8 [0114], last two sentences} of each of the N slave devices {“to the particular slave nodes 104”, see Fig. 8, [0114], last two sentences} when receiving the specific instruction {“synchronization frames”, see Fig. 7 [0104], 2nd sentence}, such that the N slave devices are controlled to be in a through state {“dynamic removal of data from a downstream transmission and insertion of data into an upstream transmission [via a through state]” (see Fig. 9 [0115], 1st sentence) via state change in either MUX or DEMUX per node/master (“demultiplexer (DEMUX) 168 may demultiplex the preamble, synchronization frames, and data from the receive stream.”, [0104], 2nd sentence; or “multiplexer (MUX) 168 may multiplex a preamble from the preamble circuitry 156, synchronization frames, and data into a stream for transmission” ([0102], last two sentences)}.
Oreggia/Chen/De Renzis/Snyder and Kessler are analogous because they are from the same field of endeavor, master/slave device communications.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Oreggia/Chen/De Renzis/Snyder and Kessler before him or her, to modify Oreggia/Chen/De Renzis/Snyder’s system incorporating Kessler’s “upstream transceiver 122 and the downstream transceiver 124 may communicate with bus protocol circuitry 126, and the bus protocol circuitry 126” (see Fig. 2, [0058], 1st sentence).
The suggestion/motivation for doing so would have been to implement number of wires reduction around conventional centralized processor approach, thus enabling faster localized processing as information is globally distributed via the bus. (Kessler [0216], paraphrased).
Therefore, it would have been obvious to combine Kessler with Oreggia/Chen/De Renzis/Snyder to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Oreggia discloses wherein:
a) when one of the N slave devices is in a through state {see Fig. 2, “slave BMIC 213SA [through state] decodes the received Isolated SPI signal into the three-pin signal”, [0041], 2nd sentence}, coupling an input port {input port “I/O pins labeled as SDO, ISOLP_SDI”, see Fig. 2, [0037], 2nd sentence} and an output port of the corresponding slave device together to form a first pathway {“form a first [pathway] Isolated SPI interface for communication with a previous BMIC 213”, see Fig. 2, [0038]};
and b) the linked pathway is formed by coupling the first pathways {see Fig. 2, “the I/O pins ISOLP_SDI and ISOLM_NCS of each slave BMIC 213S form a first Isolated SPI interface for [respective path ways] communication with a previous BMIC 213”, [0038]} of the plurality of slave devices in series {see Fig. 2, “with a previous BMIC 213 in the [series] daisy chain (or the master BMIC 213M)”, [0038]}.
As per claim 3, the rejection of claim 1 is incorporated and Oreggia discloses wherein:
a) the master device transmits a specific instruction indicating {see Fig. 2, “thereby recovering the [specific instruction] request message from the MCU 211) and processes the received request message”, [0041], 3rd sentence} that a synchronization signal needs to be transmitted {“three-pin output signal that includes a first data signal labeled as DIRECT, a second data signal labeled as REVERSE, and a [needed] synchronization signal labeled as SCK”, see Fig. 4a, [0047]};
b) each of the N slave devices {“Each of the slave BMICs 213SB and 213SC receives the relayed Isolated SPI signal”, [0042], 1st sentence} when receiving the specific instruction serves as a current slave device {see Fig. 2, “internal processing of the received Isolated SPI signal in the [current] slave BMICs 213SB and 213SC”, see Fig. 2, [0042]};
Chen discloses c) the current slave device is controlled to be in a first mode {see Figs. 6D and 7a, “peak current mode boost converter controller”, [0119], 1st sentence} to receive the specific instruction from the master device or a previous slave device {see Figs. 6B and 7E, “adjustment signal Vout_adj to DC/DC converter 70 over control path 124.” ([0113], last sentence) for setting “peak current mode”}, and to forward the specific instruction to a subsequent slave device {see Fig. 5a, “each LED string to current driver 80 may be referred to as a headroom voltage”, [0101], 1st sentence};
and d) the current slave device is controlled to be in a second mode {see Figs. 7E and 8a, “a first (single-phase) mode for supporting light loads and a second (dual-phase mode) for supporting larger loads.”, [0132], 2nd sentence}, an input port {“input port configured to receive input voltage Vin, an input capacitor C1 coupled across the input port between node n1 and the ground power supply line” coupled as illustrated Fig. 7a, [0120] 1st sentence} and an output port of the current slave device are coupled to form a first pathway {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence}, and the current slave device is in a through state {see Figs. 4b and 7a, “Gate driver output signal GDRV1 may be reasserted [through state] at the beginning of the next switching cycle to reactivate.”, [0122] 4th sentence}.
As per claim 4, the rejection of claim 2 is incorporated and Oreggia discloses wherein the coupling the input port and the output port of the slave device comprises connecting the input port {input port “I/O pins labeled as SDO, ISOLP_SDI”, see Fig. 2, [0037], 2nd sentence} and the output port of the slave device directly {“form a first [pathway] Isolated SPI interface for communication with a previous BMIC 213”, see Fig. 2, [0038]}, or connecting the input port and the output port of the slave device through a buffer {Examiner’s note, recitation the phrase “or connecting the input port” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}.
As per claim 5, the rejection of claim 1 is incorporated and Chen discloses wherein each of the plurality of slave devices comprises a control unit {see Figs. 11a and 11b, “[slave device] in-rush current controller 320”, [0160], last two sentences}, wherein:
a) when one of the N slave devices is in a first mode {see Figs. 6D and 7a, a first slave device mode as configured by “peak current mode boost converter controller”, [0119], 1st sentence)}, an input port {“input port configured to receive input voltage Vin, an input capacitor C1 coupled across the input port between node n1 and the ground power supply line” coupled as illustrated Fig. 7a, [0120] 1st sentence} and an output port of the corresponding slave device are connected through the control unit {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence};
and b) when one of the N slave devices is in a second mode {see Figs. 7E and 8a, “a first (single-phase) mode for supporting light loads and a second (dual-phase mode) for supporting larger loads.”, [0132], 2nd sentence}, the input port {“input port configured to receive input voltage Vin, an input capacitor C1 coupled across the input port between node n1 and the ground power supply line” coupled as illustrated Fig. 7a, [0120] 1st sentence} and output port of the corresponding slave device are connected directly {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence}, or the input port and the output port of the corresponding slave device are connected through a buffer to form a first pathway {(Examiner’s note, recitation the phrase “or connecting the input port” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}.
As per claim 6, the rejection of claim 1 is incorporated and Oreggia discloses wherein a control unit in each of the N slave device {control unit “digital control circuit 103 of the slave BMIC 213SA converts”, see Fig. 2, [0041], 3rd sentence} receives the synchronization signal {“signal SCK may be referred to as the synchronization signal of the three-pin signal”, see Fig. 4a, [0049] last sentence} and performs synchronization operation according to the synchronization signal {see Figs. 2a and 4D, “signals labeled as DIRECT, REVERSE, and SCK at the bottom of FIG. 4D”, [0053], 3rd sentence}.
As per claim 7, the rejection of claim 1 is incorporated and Oreggia discloses wherein the synchronization signal is transmitted by the master device {FIG. 2, “master BMIC 213M communicates with the MCU 211 using the standard SPI protocol, and connects with the MCU 211 through I/O pins labeled as SDO, ISOLP_SDI, SCK”, [0037] 2nd sentence} or by an external circuit {Examiner’s note, recitation the phrase “or by an external circuit” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}.
As per claim 8, the rejection of claim 1 is incorporated and Chen discloses wherein after a predetermined time has elapsed from a moment {see Fig. 4E, “optionally a predetermined delay time may impose several technical requirements”, [0098], 1st sentence} when the N slave devices receive the synchronization signal {FIG. 4C, “when signal BL_EN is asserted” by the master device, [0078] 1st sentence}, the N slave devices are controlled to be in a first mode {see Figs. 6D and 7a, “peak current mode boost converter controller”, [0119], 1st sentence}, such that an input port {“input port configured to receive input voltage Vin, an input capacitor C1 coupled across the input port between node n1 and the ground power supply line” coupled as illustrated Fig. 7a, [0120] 1st sentence} and an output port of each of the N slave devices {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence} are connected through a control unit {see Figs. 11a and 11b, “[slave device] in-rush current controller 320”, [0160], last two sentences}, wherein the predetermined time is greater than or equal to zero {see Fig. 4E, “impose several technical requirements” infers a time greater than zero, [0098], 1st sentence}.
As per claim 9, the rejection of claim 1 is incorporated and Chen discloses wherein the transmitting the synchronization signal occurs after a first time has elapsed from a moment {see Fig. 4E, “optionally a predetermined delay time may impose several technical requirements”, [0098], 1st sentence} when the master device transmits a specific instruction indicating that the synchronization signal needs to be transmitted {see Fig. 4E, “proper synchronization of the two backlight driver ICs may also require receipt of the externally supplied LSYNC signal”, [0098]}, wherein the first time is greater than or equal to a time period {see Fig. 4C, “will use PLL 72-2 to time a desired delay (see Tdelay in FIG. 4C) such that channel 1 of the second backlight driver 64-2 will start with the correct phase delay/offset”, [0078], 2nd sentence} from a moment when the master device transmits the specific instruction {see Fig. 6B, “headroom feedforward control circuit 122 may receive the stored brightness code/command directly from [master device] brightness register 90”, [0113], 2nd sentence} to a moment when the N slave devices are in the through state {“duty cycle of the PWM signals can be modulated to control the period of time during which each LED string is [through state] turned on”, see Fig. 4b, [0075]}.
As per claim 10, the rejection of claim 5 is incorporated and Chen discloses wherein each of the N slave devices further comprises: a) a mode selection circuit {see Fig. 8c, “converter 70 may [selection] transition between a single-phase operational mode 160 and a dual-phase operational mode 164”, [0136], 2nd sentence}, having a first end coupled to the input port of the corresponding slave device {see Fig. 11a, “between the input port at which input voltage Vin is received and input capacitor C1”, [0160], last two sentences}, and a second end selectively coupled to the output port of the corresponding slave device {“used in a boost converter 70 with any number of phases [any number of output ports/loads] (e.g., for a single-phase boost converter, a dual-phase boost converter, or a generic N-phase boost converter where N>2”, [0150], last sentence} or a first end of a control unit {Examiner’s note, recitation the phrase “or a first end of a control unit” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}, wherein a second end of the control unit is coupled to the output port of the corresponding slave device {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence};
and b) wherein the mode selection circuit controlled by the control unit is configured {see Fig. 7a, “arrangement of boost converter 70 that is configured in a single-phase multi-switch arrangement. The single-phase multi-switch configuration may be particularly suitable for medium load applications”, [0123], last sentence”, [0123] last sentence} to control the corresponding slave device to operate in one of the first mode and the second mode {see Fig. 7E, “multi-phase multi-switch arrangement”, [0127] 1st sentence}.
As per claim 11, the rejection of claim 10 is incorporated and Chen discloses wherein the mode selection circuit comprises a selection switch {see Fig. 8c, “converter 70 may [a selection switching] transition between a single-phase operational mode 160 and a dual-phase operational mode 164”, [0136], 2nd sentence}.
As per claim 12, the rejection of claim 10 is incorporated and Chen discloses wherein in the second mode, the second end of the mode selection circuit is connected to the output port of the corresponding slave device {see Fig. 8c, “converter 70 may [a selection switching] transition between a single-phase operational mode 160 and a dual-phase operational mode 164”, [0136], 2nd sentence}, or is coupled to the output port of the corresponding slave device through a buffer {Examiner’s note, recitation the phrase “or output port of the corresponding slave device” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}.
As per claim 13, the rejection of claim 10 is incorporated and Chen discloses wherein in the first mode, the second end of the mode selection circuit is connected to the first end of the control unit {see Figs. 7a and 7e, output 70” ([0120] last sentence}.
As per claim 14, the rejection of claim 5 is incorporated and Chen discloses wherein each of the N slave devices further comprises: a) a mode selection circuit {see Fig. 8c, “converter 70 may [selection] transition between a single-phase operational mode 160 and a dual-phase operational mode 164”, [0136], 2nd sentence}, having a first end coupled to the output port of the corresponding slave device {see Fig. 11a, “between the input port at which input voltage Vin is received and input capacitor C1”, [0160], last two sentences}, and a second end selectively coupled {see Fig. 11B, “controller 320 may be provided with a detection resistor Rdet coupled between the gate and source terminals of transistor 322”, [0162] 1st sentence} to the input port of the corresponding slave device or a first end of a control unit {Examiner’s note, recitation the phrase “or connecting the input port” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}, wherein a second end of the control unit is coupled to the input port of the corresponding slave device {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence};
and b) wherein the mode selection circuit controlled by the control unit is configured to control the corresponding slave device {see Figs. 11a and 11b, “[slave device] in-rush current controller 320”, [0160], last two sentences} to operate in one of the first mode and the second mode {see Fig. 8c, “converter 70 may [a selection switching] transition between a single-phase operational mode 160 and a dual-phase operational mode 164”, [0136], 2nd sentence}.
As per claim 15, the rejection of claim 14 is incorporated and Chen discloses wherein in the second mode, the second end of the mode selection circuit is connected to the input port of the corresponding slave device {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence}, or is coupled to the input port of the corresponding slave device through a buffer {Examiner’s note, recitation the phrase “or connecting the input port” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim}.
As per claim 16, the rejection of claim 14 is incorporated and Chen discloses wherein in the first mode, the second end of the mode selection circuit is connected to the first end of the control unit {see Figs. 7a and 7e, output port node “n3” and respective load “or Ln is coupled to output node n3 via diode 142-n” ([0128]) where “Node n3 serves as the output port for boost converter 70” ([0120] last sentence}.
As per claim 17, the rejection of claim 14 is incorporated and Chen discloses wherein the mode selection circuit comprises a selection switch {see Fig. 8c, “converter 70 may [a selection switching] transition between a single-phase operational mode 160 and a dual-phase operational mode 164”, [0136], 2nd sentence}.
As per claim 18, the rejection of claim 1 is incorporated and Chen discloses wherein:
a) each slave device is configured for driving at least one light-emitting diode (LED) string {“duty cycle of the PWM signals can be modulated to control the period of time during which each LED string is [through state] turned on”, see Fig. 4b, [0075]};
b) when a brightness of one LED string needs to be changed {“global brightness throttling method is provided to handle an LED short fault without having to turn off a defective LED string”, see Fig. 5a, [0105], 1st sentence}, the slave device corresponding to the LED string changes the brightness of the LED string {“how LED current driver 80 may include a maximum brightness limit control circuit 92”, see Fig. 5a and 5b, [0105]} after delaying for a second time from a rising edge {E or a falling edge {Examiner’s note, recitation the phrase “or connecting the input port” renders this dependent claim as a Markush claim, thus the reference needs to disclose at least one member in the group to address the claim} of a pulse of the synchronization signal {see Figs. 5a and 5b, “may receive the brightness command from brightness register 90, may receive the fault information from fault detection circuit 86 via path 88”, [0105], last sentence};
and c) the second time is greater than or equal to zero {see Fig. 4E, “impose several technical requirements” infers a time greater than zero per LED string, [0098], 1st sentence}.
As per claim 19, the rejection of claim 1 is incorporated and Chen discloses wherein:
a) each slave device is configured for driving at least one LED string {“duty cycle of the PWM signals can be modulated to control the period of time during which each LED string is [through state] turned on”, see Fig. 4b, [0075]};
b) the slave device is configured to generate a frequency of an LED current control signal {see Fig. 5c, “throttle coefficient K_throttle might be set to 5%, to 7.5%, to 10%, to 12.5%, to 15%, or to any suitable level between 1-20%”, [0108], 2nd sentence} for driving an LED string according to a frequency of the synchronization signal {see Fig. 5C, “the PWM frequency of the LED current driver 80”, [0110], 1st sentence}, in order to improve accuracy of an LED current in one period of the synchronization signal {see Fig. 5c, “sufficient headroom margin so that the LED current driver is able to deliver an accurate target current to each of the connected LED strings”, [0109], 1st sentence}; and
c) the frequency of the LED current control signal is equal to a product of a first coefficient {see Fig. 5c, “suitable [product] level between 1-20% to globally adjust the maximum brightness under a detected fault condition”, [0108], 2nd sentence} and the frequency of the synchronization signal, and the first coefficient is a positive integer {see Fig. 5c, “sufficient headroom margin so that the LED current driver is able to deliver an accurate target current to each of the connected LED strings”, [0109], 1st sentence}.
As per claim 20, the rejection of claim 1 is incorporated and Oreggia discloses a serial communication system, comprising the method of claim 1, wherein {“convert the three-pin signal into the Isolated [serial peripheral interface] SPI signal”, [0005] last sentence}:
a) the master device {“When the BMIC 100 works in master mode”, see Figs. 1 and 2, [0028], 1st sentence} and the N slave devices are coupled in series in sequence {“The slave BMICs 213S are connected in a daisy chain configuration”, see Figs. 1 and 2, as claimed to the master device, [0038], 2nd sentence}; and b) the N slave devices {“ISOLP_SDI and ISOLM_NCS of each slave BMIC 213S form a first Isolated SPI interface”, see Fig. 2 [0038]} receive the synchronization signal at the same time {“synchronization signal labeled as SCK in FIG. 4A”, [0047], last sentence}.
Response to Arguments
Applicant’s arguments, filed on 06/17/2026, have been considered however rendered moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “serial communication”, “specific instruction”, or “slave devices”: US 11132323 B2, US 11704274 B2, US 10949365 B2, US 10872049 B2, US 10454478 B2, US 9720874 B2, US 20230206830 A1, US 10949365 B2, US 20170220502 A1, and US 6434634 B1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.B./
Examiner, rt Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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