Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 were previously examined.
Claim 19 are amended on January 2, 2026.
Claims 1-20 are pending in this action.
Response to Arguments
Applicant's arguments, see under “35 USC 101” filed January 2, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
On pages 9-10, Applicant indicated that Independent claim 1 recites a particular integration of features into a practical application, including, for example, "circuitry ... operable to: store an inversion indication bit using a one-time programmable memory element of the array of one-time programmable memory elements," where "the inversion indication bit indicating whether the plurality of one-time programmable memory elements store the plurality of address bits or the inversion of the plurality of address bits," as recited in independent claim 1. For example, regarding independent claim 1, the feature to "store an inversion indication bit using a one-time programmable memory element of the array of one-time programmable memory elements," improves the functioning of an apparatus, such as a memory system. See, e.g., Specification ,-i,i [0012]-[0014]. Therefore, for at least the reason that independent claim 1 includes features that improve the functioning of a memory system, any alleged judicial exception included in independent…
In Responses:
Examiner disagreed because a method of “determine whether to store a second indication…” is based on mental or mathematical abstract calculation. The reason is that when mental/mathematical is to determine NOT to store a second indication at all then the following limitations “store the second indication of the address…store an inversion indication…address bits” is not even performed. Therefore, the independent claim does not improve the functioning of an apparatus at all.
Examiner disagreed because a method of “determine whether to store a second indication…” is not based on the received first indication of a failure. It is based on mental or mathematical abstract calculation. Therefore, the independent claim does not improve the functioning of an apparatus at all.
Examiner disagreed because a method of “storing the a second indication” and/or “storing an inversion indication” into a memory such as “one-time programmable memory elements” do not improve the functioning of an apparatus at all. The reason is the stored second indication” and/or “stored an inversion indication” is/are not being used for any useful purpose for improvement of functioning or functionality of an apparatus at all.
As such, the rejection is maintained.
Applicant's arguments, see under “35 USC 112b” filed January 2, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
On pages 11-12, Applicant argued that the original person skill in the art would understand what is claimed because of the specification.
As the Specification explains:
a memory system may store an address of a failed access line or an inversion of the address based on a quantity of bits with a logic value (e.g., a logic state, a bit value). In some examples, if an address has fewer bits with a logic 1 value than bits with a logic 0 value, the memory system may store the address by setting some OTP elements to indicate the logic 1 values of the address and maintaining other OTP elements in an original state to indicate the logic 0 values of the address. In some other examples, if the address has more bits with a logic 1 value than bits with a logic 0 value, the memory system may store an inversion of the address, such that logic 1 values are inverted to logic 0 values, and vice versa, by setting OTP elements to indicate the inverted logic 0 values.
In Responses:
Examiner disagreed because the paragraph above do not even recite or mention about “a second indication” at all. It does not mention the reason for determining whether to store a second indication using a plurality of address bits…. Therefore, the original person skill in the art would NOT understand what is claimed based on the paragraph above.
Applicant’s arguments:
On pages 11-12, Applicant argued that the original person skill in the art would understand what is claimed because of the specification.
As the Specification explains:
In some other examples, if the address has more bits with a logic 1 value than bits with a logic 0 value, the memory system may store an inversion of the address, such that logic 1 values are inverted to logic 0 values, and vice versa, by setting OTP elements to indicate the inverted logic 0 values. The memory system may also store an inversion bit (e.g., a fuse bit inversion (FBI) bit) to indicate whether an address is inverted. To read the OTP elements, the memory system may interpret an address as inverted or non-inverted based on a value of the inversion bit.
In Responses:
Examiner disagreed because the paragraph above do not even recite or mention about “a second indication” at all. It does not mention the reason for determining whether to store a second indication using a plurality of address bits…. Therefore, the original person skill in the art would NOT understand what is claimed based on the paragraph above.
As such, the rejection is maintained.
Applicant's arguments, see under “35 USC 103” filed January 2, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments:
On pages 13-14, Applicant argued that the prior arts of record disclose a method of “generating an inversion flag signal based on a number of changed bits of address data in a first address signal and a second address signal fails.” However, the prior art fails to teach or suggest to "receive a first indication of a failure associated with an address of the memory array," as recited in independent claim 1.
In Responses:
Examiner disagreed because claim 1 only recites “receive a fist indication of a failure associated with an address”. However, claim 1 does not clearly explain what is “a first indication of a failure associated with an address” or how “a first indication of a failure associated with an address” is generated. Therefore, the prior art of Jin discloses an inversion flag signal as an indication of failure associated with address.
It is suggested that Applicant amend the claim to clarify “a fist indication of a failure associated with an address” in order to overcome the rejection.
Applicant’s arguments:
On pages 13-14, Applicant argued that the prior arts of record disclose a “one-time programmable memory elements”
In Responses:
Examiner disagreed because “one-time programmable memory elements” is just a memory for storing data. As such, the prior arts of record disclose a memory for storing data.
Examiner disagreed because the recited claims do not recited such as “program the second indication using one-time programmable memory elements” for the first time. It is well-known in the art that “one-time programmable memory elements” cannot “store a second indication” after it has been programmed first time.
It appears that the second indication cannot store in the one-time programmable memory elements” when “one-time programmable memory elements” has been programmed previously.
As such, the rejection is maintained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-8, 11, 14-19, are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
It is noted that claim 2-3, 9-10, 12, 13 and 20 are not rejected under 101 abstract.
In analyzing under step 1, is the claim to a process, machine manufacture or composition of matter? Yes.
In analyzing under step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes.
The claim(s) 1, 11 and 19 recite(s) the abstract limitations such as “receive a first indication of a failure associated with an address of the memory array; determine whether to store a second indication of the address using a plurality of address bits associated with the address or an inversion of the plurality of address bits based at least in part on a quantity of the plurality of address bits that have a bit value; store the second indication of the address using a plurality of one-time programmable memory elements of the array of one-time programmable memory elements based at least in part on determining whether to store the second indication of the address; and store an inversion indication bit using a one-time programmable memory element of the array of one-time programmable memory elements, the inversion indication bit indicating whether the plurality of one-time programmable memory elements store the plurality of address bits or the inversion of the plurality of address bits” is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mental processes and/or mathematical processes but for the recitation of generic computer processor such as “an apparatus, comprising: a memory array comprising a plurality of memory cells and a plurality of access lines coupled with the plurality of memory cells; an array of one-time programmable memory elements; and circuitry coupled with the memory array and the array of one-time programmable memory elements and operable to:” (see claim 1) and “A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing system to” (see claim 19)
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mathematical processes or mental processes but for the recitation of generic computer components and software module, then it falls within the “Mental Processes” and/or “Mathematical processes” grouping of abstract ideas.
The mental processes with a generic processor (1) can receive “a first indication of a failure” and (2) can determine whether to store a second indication or an inversion indication based on mathematical algorithm and (3) then store a second indication and/or an inversion indication.
The mental processes with a generic processor can output a third indication to indicate a repair operation (see claim 4).
The mental processes with a generic processor can receive a third indication to indicate to enter a mode and to can response an acknowledge that it has enter a mode (see claim 5)
The mental processes with a generic processor can output a third indication to indicate that it has exited a mode (see claim 6).
The mental processes with a generic processor can perform a summation bits that satisfies a threshold based on a mathematical calculation.
Claims 1, 11 and 19 do not provide any improvement for generic processes which is well-known to comprise a memory array, and a programmable memory device.
Accordingly, the claim recites an abstract limitation.
This judicial exception is not integrated into a practical application under Step 2A Prong 2. The recited steps of "receiving a first indication” or “store second indication…or an inversion indication…”are extra-solution activity to the judicial exception, and hence these features are not indicative of integration into a practical application.
In analyzing under step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO.
This judicial exception is not integrated into a practical application because the claims recite a generic processor such as ““an apparatus, comprising: a memory array comprising a plurality of memory cells and a plurality of access lines coupled with the plurality of memory cells; an array of one-time programmable memory elements; and circuitry coupled with the memory array and the array of one-time programmable memory elements and operable to:” (see claim 1) and “A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing system to” (see claim 19) for determining whether to store or not to store a second indication or an inversion indication data.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because a generic processor and software module which are high level of generality determination of storing data.
Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea.
In analyzing under step 2B, does the claim recite additional elements that amount to significantly more than the judicial exception? NO
Claims 1, 4-8, 11, 14-19 do not recite any additional elements except a generic for determining whether to store or not to store.
Accordingly, the additional generic elements do not amount to significantly more than the judicial exception storing determination.
The claim is directed to an abstract idea.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11 and 19 recite a limitation such as “determine whether to store a second indication of the address using a plurality of address bits associated with the address or an inversion of the plurality of address bits based at least in part on a quantity of the plurality of address bits that have a bit value”
The recited limitation such as “a second indication…” renders this limitation indefinite because Applicant fails to provide a method of obtaining a second indication. As such, it is unclear how to obtain a second indication.
The recited limitation such as “an inversion indication…” renders this limitation indefinite because Applicant fails to provide a method of obtaining a second indication. As such, it is unclear how to obtain an inversion.
The recited condition limitation such as “determine whether to store a second indication…or an inversion” renders this limitation indefinite because it is unclear what happen to the remaining of claim when it is to determine NOT to store both a second indication and also an inversion indication. As such, it is unclear if any other steps in the recited claims are performing.
Claim 1, 11 and 19 recites the limitation "using a plurality of address bits associated with the address". There is insufficient antecedent basis for this limitation in the claim. It is unclear where the address bits. It is unclear how to use the address bits for a second indication and an inversion indication.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11 19 and is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 2024/0,046,972), in view of Gervasi (US 2006/0,259,678)
As per claim 1:
As per claim 11:
As per claim 19:
Kim discloses:
An apparatus, comprising: a memory array comprising a plurality of memory cells and a plurality of access lines coupled with the plurality of memory cells; an array of one-time programmable memory elements; and circuitry coupled with the memory array and the array of one-time programmable memory elements and operable to:
A method, comprising:
A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing system to:
receive a first indication of a failure associated with an address of the memory array;
(Ji [0023] In some embodiments, the transmission control circuit 101 may generate the inversion flag signal ABI based on a difference between the first address signal and the second address signal. The difference may be the number of changed bits of the address data in the first address signal and the second address signal)
determine whether to store a second indication of the address using a plurality of address bits associated with the address or an inversion of the plurality of address bits based at least in part on a quantity of the plurality of address bits that have a bit value;
(Ji [0023] In some embodiments, the transmission control circuit 101 may generate the inversion flag signal ABI based on a difference between the first address signal and the second address signal. The difference may be the number of changed bits of the address data in the first address signal and the second address signal)
(Ji [0023] In some embodiments, the transmission control circuit 101 may generate the inversion flag signal ABI based on a difference between the first address signal and the second address signal. The difference may be the number of changed bits of the address data in the first address signal and the second address signal)
(Ji [0023] In some embodiments, the transmission control circuit 101 may generate the inversion flag signal ABI based on a difference between the first address signal and the second address signal. The difference may be the number of changed bits of the address data in the first address signal and the second address signal)
(Ji [0023] …selection circuit 102 is further configured to, in a case where the number of changed bits is greater than or equal to the predetermined value, invert the second address signal to obtain the address inverted signal and output the address inverted signal, and in a case where the number of changed bits is smaller than the predetermined value, to directly output the second address signal)
Ji does not disclose to store an inversion indication.
Gervasi discloses:
store an inversion indication
(Gervasi, [0035] Fig. 5…to program the address inversion control bit to enable address inversion)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Gervasi’s method of program the inversion indication control bit into the system in order to control the inversion of address of Ji.
(Gervasi, [0035] Fig. 5…to program the address inversion control bit to enable address inversion)
Allowable Subject Matter
Claims 2, 8, 9, 12, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if applicant can overcome other rejection above. Claims 3 and 13 are also objected due to dependency of objected claims 2 and 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kumar et al. (US 2020/0,243,153) comparator circuit 108 operates to compare the encoded address EAddr to the row address RAddr and assert an output error Flag when the addresses do not match.
Kim (US 2013/0,111,102) discloses a method of determining the number of bit changes in each group, and provides the third flag signal FLAG3 indicating whether the number of bit changes is greater than half of address width of the current address signal ADD. …, the inversion control unit 682 may provide to the first and second selective address inversion units 683, 684 the third flag signal FLAG3 with a low level, when the number of bit changes in each group is not greater than the address width of the address signal ADD. [0147] The first selective address inversion unit 683 selectively either inverts or maintains (non-inverts) the current address signal ADD continuously provided from input buffer unit 681 in response to the third flag signal…”
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111
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