Tech Center 2100 • Art Units: 2111 2112 2114 2117 2137
This examiner grants 87% of resolved cases
Examiner Thien Dang Nguyen operates within Art Unit 2111 of Tech Center 2100, where they have managed 713 resolved cases. The data shows an allowance rate of 87.4 percent, suggesting a high frequency of successful outcomes for applicants. For those seeking to clarify their applications, the median days to allowance stands at 735. This timeline provides a benchmark for practitioners to set expectations when filing in this unit.
The use of examiner interviews appears to be a productive strategy in this profile. An interview lift of 11.7 percent indicates that engaging directly with the examiner correlates with a higher probability of allowance compared to cases without such interaction. Practitioners should consider this 11.7 percent increase when deciding on prosecution tactics. The 87.4 percent baseline allowance rate already suggests a favorable environment, but the lift suggests that verbal communication can resolve remaining hurdles.
With 713 resolved cases, the examiner's performance metrics are well-established and offer a reliable foundation for strategic planning. The 735-day median to allowance is a key figure for managing client timelines. Overall, the combination of a high allowance rate and a positive interview lift makes this a relatively predictable profile for patent prosecution in Tech Center 2100.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 19068297 | METHOD FOR DETERMINING AUXILIARY BIT OF POLAR CODE AND APPARATUS | Non-Final OA | HUAWEI TECHNOLOGIES CO., LTD. |
| 19021479 | Rebuilding Encoded Data Slices in Accordance with a Reduced Rebuild Threshold | Non-Final OA | Pure Storage, Inc. |
| 19177212 | VIRTUAL DISTILLATION FOR QUANTUM ERROR MITIGATION | Non-Final OA | Google LLC. |
| 18920748 | TECHNIQUES FOR RADIO ACCESS NETWORK SIGNALING FOR FORWARD ERROR CORRECTION AWARENESS AND PACKET DATA UNIT SET INFORMATION MARKING | Non-Final OA | QUALCOMM Incorporated |
| 18459185 | APPARATUS, SYSTEM, AND METHOD OF A PRE FORWARD ERROR CORRECTION (FEC) (PRE-FEC) PADDING | Non-Final OA | Intel Corporation |
| 18812638 | ERROR CORRECTION ENCODING DEVICE, ERROR CORRECTION DECODING DEVICE, ERROR CORRECTION ENCODING METHOD, ERROR CORRECTION DECODING METHOD, CONTROL CIRCUIT, AND STORAGE MEDIUM | Non-Final OA | Mitsubishi Electric Corporation |
| 18943077 | METHODS, SYSTEMS AND APPARATUS FOR SCHEDULING OF HYBRID AUTOMATIC REPEAT REQUEST (HARQ) FEEDBACK | Non-Final OA | INTERDIGITAL PATENT HOLDINGS, INC. |
| 18985491 | METHODS AND SYSTEMS FOR DATA TRANSMISSION | Final Rejection | MARVELL ASIA PTE LTD |
| 19077770 | ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME | Non-Final OA | SK hynix Inc. |
| 19038044 | SEMICONDUCTOR DEVICE PERFORMING DATA READ OPERATION AND CONTROLLER CONTROLLING THE SAME | Non-Final OA | SK hynix Inc. |
| 19071695 | MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM | Non-Final OA | Kioxia Corporation |
| 19201781 | BYPASSING ITERATIONS IN A BIT FLIPPING DECODER USING A LEAST RELIABLE BIT ENERGY FUNCTION | Non-Final OA | Micron Technology, Inc. |
| 18783321 | ERROR DETECTION FOR ACTIVATED PAGES IN A MEMORY DEVICE | Non-Final OA | Micron Technology, Inc. |
| 18967975 | TEST IMPLEMENTATION | Final Rejection | STMicroelectronics International N.V. |
| 19074196 | Systems and Methods of Inserting Idles Within Packets to Reduce Latency | Non-Final OA | Cisco Technology, Inc. |
| 18314125 | Outer-Loop Adaptation | Non-Final OA | Parallel Wireless, Inc. |
| 18879990 | SYSTEM AND METHOD FOR POLAR DECODING | Final Rejection | JIO PLATFORMS LIMITED |
| 18616440 | QUANTUM HOMOMORPHIC ENCRYPTION SYSTEM AND METHOD | Final Rejection | KOREA INSTITUTE OF SCIENCE & TECHNOLOGY INFORMATION |
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