DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. US 2022/0415647 in view of Shih et al. US 10147611.
Regarding claim 1, Su et al. Figs. 2B-2K and [0012]-[0033] disclose a method for preparing a semiconductor device structure, comprising:
forming a target layer 101a, 101b [0013];
forming a first energy-sensitive pattern 104a [0015] over the target layer 101a, 101b;
forming a lining layer 105 [0016] covering the first energy-sensitive pattern 104a; forming a second energy-sensitive pattern 106 [0017] over the lining layer 105, wherein the first energy-sensitive pattern 104a and the second energy-sensitive pattern 106 are staggered Fig. 2E;
performing an etching process [0018] to form a first opening 119 and a
second opening 109 in the target layer 101a, wherein the first opening 119 and the second 109 opening have different depths [0024]-[0032].
Su et al. do not expressly disclose the target layer being formed over a semiconductor substrate; performing a first energy treating process to transform an upper portion of the first energy-sensitive pattern into a first treated portion; and performing a second energy treating process to transform an upper portion of the second energy-sensitive pattern into a second treated portion.
Shih et al. Figs. 6-7 and col. 6, lines 25-64 teach a target layer 202 being formed over a semiconductor substrate 200; performing a first energy treating process to transform an upper portion of a first energy-sensitive pattern 212 into a first treated portion 208; and performing a second energy treating process col. 6, lines 45-64 to transform an upper portion 244 of the second energy-sensitive pattern 242 into a second treated portion 244.
Therefore, it would have been obvious to person of ordinary skill in the art, before the effective filing date of the claimed invention to incorporate the energy treating processes and the substrate of Shih et al. into the method of Su et al. in order to arrive at the expected result of giving the manufacturer more control over the process of manufacture by introducing more hard mask layers which will change the etching rate while manufacturing the device and allowing for a more structurally sound device by performing the steps on a substrate with reasonable expectation of success.
Regarding claim 2, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Shih et al. teach wherein an etching rate of the treated portion 244, 208 is different from an etching rate of the first energy-sensitive pattern 212 during the etching process. (Shih et al. col. 5, lines 28-41 states “...the first sacrificial layer 210 can include organic materials, and the organic materials can include photosensitive material(s) or non-photosensitive material(s), but the disclosure is not limited thereto, The mask layer 208 may provide improved etch selectivity and/or antireflective properties for removing the first sacrificial layer 210,”; antireflective materials and photosensitive materials have different etch rates)
Regarding claim 3, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Su et al. Fig. 2J teach wherein the first opening 119 and the second opening 109 are staggered (e.g. first opening 119 and second opening 109 are seen having different depths and being adjacent to each other and are staggered).
Regarding claim 4, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Su et al. Fig. 2E teach wherein the second energy-sensitive pattern 106 is separated from the first energy-sensitive pattern 104a by the lining layer 105.
Regarding claim 5, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Su et al. Fig. 2D teach wherein a top surface 104t and sidewalls sidewalls of 104a of the first energy-sensitive pattern 104a are covered by the lining layer 105.
Regarding claim 6, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Su et al. Fig. 2E teach wherein a bottom surface 106 of the second energy-sensitive pattern 106 is higher than a bottom surface 104a of the first energy-sensitive pattern 104a, and a top surface 106 of the second energy-sensitive pattern 106 is higher than a top surface 104a of the first energy-sensitive pattern 104a.
Regarding claim 7, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Su et al. Fig. 2E teach wherein a top surface 104a of the first energy-sensitive pattern 104a is higher than a bottom surface 106 of the second energy-sensitive pattern 106.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. in view of Shih et al. as applied to claim 1 above, and further in view of Sandhu et al. US 2008/0299774.
Regarding claim 8, Su et al. in view of Shih et al. teach the method for preparing a semiconductor device structure of claim 1. Su et al. in [0015] and [0017] teach wherein the first energy-sensitive pattern 104a and the second energy-sensitive pattern 106 are made of different materials (e.g. Su [0015], "An amorphous silicon (a-Si) layer is formed on the surface 101s of the substrate;" ; the first energy-sensitive pattern is made of amorphous silicon; Su [0017], "...the clapping layer 106 can be a photoresist coating..." the second energy-sensitive pattern is made of a photoresist coating. There are known photoresist materials commonly used in etching processes other than amorphous silicon, so a method using different materials for the first and second energy-sensitive patterns would be obvious).
However, Su et al. in view of Shih et al. do not expressly teach a method wherein the lining layer includes an organic polymer material.
Sandhu et al. teach Fig. 9 and [0053] a method wherein a lining layer 170 includes an organic polymer material.
Therefore, it would have been obvious to person of ordinary skill in the art, before the effective filing date of the claimed invention to substitute the organic polymer
lining layer of Sandhu et al. into the method of Su et al. in view of Shih et al. in order to arrive at the expected result of creating a device with a lower cost of manufacture and more resistant to deformation with reasonable expectation of success.
Conclusion
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
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