Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated July 5, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed July 5, 2024 and July 25, 2024 have been
considered.
Claim Objections
Claims 3-8, 10 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 2, 9, 11-13, 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 10, 11, 13 and 20 of U.S. Patent No. 12100456 [‘456]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘456
1. A memory device, comprising: a memory string comprising a top select gate, a memory cell, and a bottom select gate, wherein the top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line; and a control circuit coupled to the first select line, the word line, and the second select line, wherein the control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage: apply an erasing voltage to the memory string in the erasing stage; apply a first voltage to the word line in a first stage of the verification stage; apply a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage; apply a first turn-on voltage to the second select line before applying the second voltage to the word line; and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.
1. A memory device, comprising: a memory string comprising a top select gate, word lines, and a bottom select gate; and a control circuit coupled to the memory string and configured to, in an erasing operation: apply an erasing voltage to the memory string; apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string; apply a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line; and apply a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.
2. The memory device of claim 1, wherein the first voltage is a pulse signal.
See claim 1. It is noted that the pulse signal is part of the applied voltage.
9. The memory device of claim 1, wherein the control circuit is further configured to: apply the first turn-on voltage to the second select line, maintaining at least until applying the second turn-on voltage to the first select line.
3. The memory device of claim 1, wherein the control circuit is further configured to: apply the first turn-on voltage to the bottom select gate, maintaining at least until applying the second turn-on voltage to the top select gate.
11. The memory device of claim 1, wherein the control circuit is further configured to apply the first turn-on voltage to the second select line, starting when the erasing voltage is applied to the memory string.
10. The memory device of claim 1, wherein the control circuit is further configured to apply the first turn-on voltage to the bottom select gate, starting when the erasing voltage is applied to the memory string.
12. A method of operating a memory device comprising a memory string, the memory string comprising a top select gate, a memory cell, and a bottom select gate, the top select gate being coupled to a first select line, the memory cell being coupled to a word line, and the bottom select gate being coupled to a second select line; the method comprising: applying an erasing voltage to the memory string in an erasing stage; applying a first voltage to the word line in a first stage of a verification stage, the verification stage being after the erasing stage; applying a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage; applying a first turn-on voltage to the second select line before applying the second voltage to the word line; and applying a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.
11. A method for operating a memory device comprising a memory string, the memory string comprising a top select gate, word lines, and a bottom select gate, the method comprising: applying an erasing voltage to the memory string; applying a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string; applying a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line; and applying a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.
13. The method of claim 12, wherein the first voltage is a pulse signal.
See claim 1. It is noted that the pulse signal is part of the applied voltage.
19. The method of claim 12, further comprising: applying the first turn-on voltage to the second select line, maintaining at least until applying the second turn-on voltage to the first select line.
13. The method of claim 11, further comprising: applying the first turn-on voltage to the bottom select gate, maintaining at least until applying the second turn-on voltage to the top select gate.
20. A memory system, comprising: a memory device comprising: a memory string comprising a top select gate, a memory cell, and a bottom select gate, the top select gate being coupled to a first select line, the memory cell being coupled to a word line, and the bottom select gate being coupled to a second select line; and a control circuit coupled to the first select line, the word line, and the second select line, wherein the control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage: apply an erasing voltage to the memory string in the erasing stage; apply a first voltage to the word line in a first stage of the verification stage; apply a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage; apply a first turn-on voltage to the second select line before applying the second voltage to the word line; and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.
20. A memory system, comprising: a memory device comprising: a memory string comprising a top select gate, word lines, and a bottom select gate; and a control circuit coupled to the memory string and configured to, in an erasing operation: apply an erasing voltage to the memory string; apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string; apply a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line; and apply a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.
As can be seen from the above table, similar to claim 1 of the present application claim 1 of patent ‘456, in that, patent '456 recites a memory string with application of an erasing stage and a verification stage, in addition, to the application of a first and second turn-on voltage applied to second and first select lines, respectively. Unlike the application, the patent only recites one verification stage; whereas, the application has two stages within the verification stage. However, the additional verification step is trivial, routine and predictable modification that does not add a new, distinct invention. Additionally, in NAND flash, after an erase pulse, it is standard practice to verify if cells have reached the target threshold voltage (Vth). A high initial verification voltage allows fast testing, while a second, lower (more precise) voltage ensures the cells have not been over-erased (which can cause read errors). Therefore, the patent protection has already been granted to the earlier filed patent application.
For similar reasons, independent claims 12 and 20 and the dependent claims 2, 9, 11, 13 and 19 are rejected over claims 1, 3, 10, 11, 13 and 20 of patent ‘456.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. [CN 113450856 A].
With respect to claim 1, Li et al. disclose a memory device, comprising: a memory string [figs. 5, 6 and 7] comprising a top select gate [SGD], a memory cell [within string of fig. 7a], and a bottom select gate [SGS], wherein the top select gate is coupled to a first select line [716], the memory cell is coupled to a word line [any of the cell coupled to the respective wordline (WL’s)], and the bottom select gate is coupled to a second select line [701]; and a control circuit (control circuit – fig. 1] coupled to the first select line, the word line, and the second select line [“…a NAND string in a block or a sub-block. each NAND string comprises a plurality of memory cells, which are connected in series at one or more drain terminal select gate transistor (referred to as SGD transistor) (the drain terminal of the NAND string connected to the bit line) and one or more source terminal select gate transistor (called SGS transistor) (at NAND string or other memory string or connected to the source end of the source line of the group of the memory unit. A select gate transistor is also referred to as a select gate. In addition, the memory unit may be arranged with a common control gate line (e.g., word line) for controlling the gate.” – 2nd par. of Specific Implementation Examples], wherein the control circuit [description of fig. 1] is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage [Abstract]: apply an erasing voltage to the memory string in the erasing stage [Abstract and description of Fig. 9]; apply a first voltage to the word line in a first stage of the verification stage [“…applying a first verify voltage VvE_bit to a first set of alternating wordlines of the block.” – description of Fig. 9]; apply a second voltage to the word line in a second stage of the verification stage [“…applying a second verify voltage VvE_norm to the first set of alternating wordlines of the block.” – description of Fig. 9H], the second stage being after the first stage, and the second voltage being lower than the first voltage [“The additional verification test (first verification test) tests the Vth of the memory unit relative to the first verification voltage, while the normal verification test (second verification test) is relative to the Vth of the second verification voltage test memory unit lower than the first verification voltage.” – 12TH par. of the Specific Implementation Examples section]; apply a first turn-on voltage to the second select line before applying the second voltage to the word line [in fig. 14, (1433) is on prior to second voltage (1414) is applied]; and apply a second turn-on voltage (1432) to the first select line after stopping application of the erasing voltage (1411) for a period of time.
With respect to claim 2, Li et al. disclose the first voltage is a pulse signal. See fig. 14.
With respect to claim 11, Li et al. disclose the control circuit is further configured to apply the first turn-on voltage to the second select line, starting when the erasing voltage is applied to the memory string. See fig. 14. In fig. 14, 1431 and 1411 occur at the same time.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. [CN 113450856 A].
With respect to claim 12, Li et al. disclose a method of operating a memory device comprising a memory string [figs. 5, 6 and 7], the memory string comprising a top select gate [SGD], a memory cell [within string of fig. 7a], and a bottom select gate [SGS], the top select gate being coupled to a first select line [716] , the memory cell being coupled to a word line [any of the cell coupled to the respective wordline (WL’s)[, and the bottom select gate being coupled to a second select line [701]; the method comprising: applying an erasing voltage to the memory string in an erasing stage [Abstract and description of Fig. 9]; applying a first voltage to the word line in a first stage of a verification stage, the verification stage being after the erasing stage [“…applying a first verify voltage VvE_bit to a first set of alternating wordlines of the block.” – description of Fig. 9]; applying a second voltage to the word line in a second stage of the verification stage [“…applying a second verify voltage VvE_norm to the first set of alternating wordlines of the block.” – description of Fig. 9H], the second stage being after the first stage, and the second voltage being lower than the first voltage [“The additional verification test (first verification test) tests the Vth of the memory unit relative to the first verification voltage, while the normal verification test (second verification test) is relative to the Vth of the second verification voltage test memory unit lower than the first verification voltage.” – 12TH par. of the Specific Implementation Examples section]; applying a first turn-on voltage to the second select line before applying the second voltage to the word line [in fig. 14, (1433) is on prior to second voltage (1414) is applied]; and applying a second turn-on voltage (1432) to the first select line after stopping application of the erasing voltage (1411) for a period of time.
With respect to claim 13, Li et al. disclose the first voltage is a pulse signal. See fig. 14.
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. [CN 113450856 A].
With respect to claim 20, Li et al. disclose a memory system, comprising: a memory device comprising: a memory string [figs. 5, 6 and 7] comprising a top select gate [SGD], a memory cell [within string of fig. 7a], and a bottom select gate [SGS], the top select gate being coupled to a first select line [716], the memory cell being coupled to a word line [any of the cell coupled to the respective wordline (WL’s)], and the bottom select gate being coupled to a second select line [701]; and a control circuit (control circuit – fig. 1] coupled to the first select line, the word line, and the second select line [“…a NAND string in a block or a sub-block. each NAND string comprises a plurality of memory cells, which are connected in series at one or more drain terminal select gate transistor (referred to as SGD transistor) (the drain terminal of the NAND string connected to the bit line) and one or more source terminal select gate transistor (called SGS transistor) (at NAND string or other memory string or connected to the source end of the source line of the group of the memory unit. A select gate transistor is also referred to as a select gate. In addition, the memory unit may be arranged with a common control gate line (e.g., word line) for controlling the gate.” – 2nd par. of Specific Implementation Examples], wherein the control circuit [description of fig. 1] is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage [Abstract]: apply an erasing voltage to the memory string in the erasing stage [Abstract and description of Fig. 9]; apply a first voltage to the word line in a first stage of the verification stage [“…applying a first verify voltage VvE_bit to a first set of alternating wordlines of the block.” – description of Fig. 9]; apply a second voltage to the word line in a second stage of the verification stage [“…applying a second verify voltage VvE_norm to the first set of alternating wordlines of the block.” – description of Fig. 9H], the second stage being after the first stage, and the second voltage being lower than the first voltage [“The additional verification test (first verification test) tests the Vth of the memory unit relative to the first verification voltage, while the normal verification test (second verification test) is relative to the Vth of the second verification voltage test memory unit lower than the first verification voltage.” – 12TH par. of the Specific Implementation Examples section]; apply a first turn-on voltage to the second select line before applying the second voltage to the word line [in fig. 14, (1433) is on prior to second voltage (1414) is applied]; and apply a second turn-on voltage (1432) to the first select line after stopping application of the erasing voltage (1411) for a period of time.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 3: The memory device of claim 1, wherein the control circuit is further configured to, in the second stage: apply a third voltage to the word line after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage.
-with respect to claim 4: The memory device of claim 1, wherein the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage at least partially overlap in timing sequence.
-with respect to claim 6: The memory device of claim 1, wherein the application of the first voltage and the application of the first turn-on voltage at least partially overlap in timing sequence.
-with respect to claim 7. The memory device of claim 1, wherein the second voltage is equal to or lower than 0 volt.
-with respect to claim 8: The memory device of claim 1, wherein the control circuit is further configured to: apply a fourth voltage to the word line in the erasing stage, wherein the second voltage is equal to or lower than the fourth voltage.
-with respect to claim 10: The memory device of claim 1, wherein the control circuit is further configured to: float the second select line before applying the first turn-on voltage to the second select line; and apply the first turn-on voltage to the second select line, starting after a floating voltage on the second select line drops.
-with respect to claim 14: The method of claim 12, further comprising: in the second stage, applying a third voltage to the word line after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage.
-with respect to claim 15: The method of claim 12, wherein the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage at least partially overlap in timing sequence.
-with respect to claim 16: The method of claim 12, wherein the application of the first voltage and the application of the first turn-on voltage at least partially overlap in timing sequence.
-with respect to claim 17: The method of claim 12, wherein the second voltage is equal to or lower than 0 volt.
-with respect to claim 18: The method of claim 12, further comprising: applying a fourth voltage to the word line in the erasing stage, wherein the second voltage is equal to or lower than the fourth voltage.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 February 4, 2026