Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US Pub # 2015/0036444).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Seo teaches a semiconductor memory device comprising: a first memory cell connected to a first word-line and a bit-line; a second memory cell connected to a second word-line and a complementary bit-line (see Fig. 1-3, 17-21 and paragraph 0045-0058, 01080121, claim 1-11 where left and right memory cell MC are first and second memory cell coupled to first wordline WL, first bitline BL and second wordline WL, second bitline BLB accordingly); and a bit-line sense amplifier connected to the bit-line and the complementary bit-line, and the bit-line sense amplifier comprising: an amplifying circuit including a P-type amplifier connected to the bit-line and the complementary bit-line and an N-type amplifier connected to a sensing bit-line and a complementary sensing bit-line (see Fig. 1-3, 17-21 and paragraph 0045-0058, 0108-0121, claim 1-11 where unit 353p, 353n are P-type amplifier, N-type amplifier accordingly), and the amplifying circuit configured to: sense a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjust a voltage of the sensing bit-line and the complementary sensing bit-line based on the voltage difference (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, Pre-sensing operation includes amplifying / reducing voltage level based on sensing voltage variation-see specially paragraph 0008); an offset cancellation circuit configured to connect the bit-line and the complementary bit-line to the complementary sensing bit-line and the sensing bit-line, respectively, based on an offset cancellation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, offset cancellation circuit OC_1, OC_2, OC is offset cancellation signal); an equalizer configured to provide a precharge voltage to the sensing bit-line and the complementary sensing bit-line based on an equalizing signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11 where E_1, E_2, E_3 are equalizer); and an isolation circuit connected between the bit-line and the sensing bit-line and between the complementary bit-line and the complementary sensing bit-line, and the isolation circuit configured to: connect the sensing bit-line and the complementary sensing bit-line equalized with the precharge voltage to the bit-line and the complementary bit-line, respectively, based on an isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, Isolation circuits ISO_1, ISO_2 which connect sensing bitline BL and complementary bit-line BLB, ISO is isolation signal).
Even though Seo teach Pre-sensing operation but silent exclusively about adjust a voltage of the sensing bit-line and the complementary sensing bit-line. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Seo where pre-sensing operation which includes amplifying / reducing voltage level i.e. adjusting voltage level based on sensing voltage variation (see specially paragraph 0008, last 3 lines) in order to have sense amplifier with improved area, sensing margin and reduced cost of memory device (see paragraph 0106, 0133).
Regarding claim 2, Seo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Seo further teaches, wherein the P-type amplifier includes: a first p-channel metal-oxide semiconductor (PMOS) transistor connected to a first supply line at a first node at which the first control signal is applied and connected to the bit-line at a third node, and including a gate connected to the complementary bit-line at a fourth node, and a second PMOS transistor connected between the first supply line and the fourth node and including a gate connected to the third node(see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108) , and wherein the N-type amplifier includes: a first n-channel metal-oxide semiconductor (NMOS) transistor connected to a second supply line at a second node at which the second control signal is applied and connected to the sensing bit-line at a fifth node, and including a gate connected to the fourth node, and a second NMOS transistor connected to the second supply line at the second node and connected to the complementary sensing bit-line at a sixth node, and including a gate connected to the third node (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0118).
Regarding claim 3, Seo teaches all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Seo further teaches, wherein the equalizer includes: a first equalizing transistor connected between a first precharge voltage node at which the precharge voltage is applied and the fifth node, and including a gate configured to receive the equalizing signal, and a second equalizing transistor connected between a second precharge voltage node at which the precharge voltage is applied and the sixth node, and including a gate configured to receive the equalizing signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058), and wherein the isolation circuit includes: a first isolation transistor connected between the third node and the fifth node, and including a gate configured to receive the isolation signal, and a second isolation transistor connected between the fourth node and the sixth node, and including a gate configured to receive the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0120).
Regarding claim 4, Seo teaches all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Seo further teaches, wherein, in a charge sharing period, the first equalizing transistor and the second equalizing transistor are configured to equalize the sensing bit-line and the complementary sensing bit-line with the precharge voltage based on the equalizing signal, and wherein, in a shifting period, the first isolation transistor and the second isolation transistor are configured to increase voltage levels of the third node and the fourth node, respectively, by connecting the sensing bit-line and the complementary sensing bit-line to the bit-line and the complementary sensing bit-line, respectively, based on the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-8).
Regarding claim 5, Seo teaches all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Seo further teaches, wherein, in the shifting period, the first isolation transistor and the second isolation transistor are turned-on in response to the isolation signal having a logic high level (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0115).
Regarding claim 6, Seo teaches all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Seo further teaches, wherein the offset cancellation circuit includes: a first offset cancellation transistor connected between the fifth node and the fourth node, and including a gate configured to receive the offset cancellation signal, and a second offset cancellation transistor connected between the sixth node and the third node, and including a gate configured to receive the offset cancellation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0120).
Regarding claim 7, Seo teaches all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Seo further teaches, wherein the bit-line sense amplifier further comprises: a first active region including a first region and a second region adjacent to the first region, wherein, in a plan view: the first region includes a horseshoe-shaped portion of the first active region, and extends in a first direction, and the second region includes rectangular portions extending in the first direction, of the first active region that are spaced apart from each other in a second direction crossing the first direction; a second active region including a rectangular shape, the second active region being spaced apart from a first side of the first active region in the first direction (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108); a third active region including a rectangular shape, the third active region being spaced apart from a second side of the first active region in the first direction; a first gate pattern extending in the second direction on the first region; a second gate pattern and a third gate pattern that extend in the second direction on the second region and are spaced apart from each other in the first direction; a fourth gate pattern having a rectangular shape on the second active region; and a fifth gate pattern having a rectangular shape on the third active region (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121).
Regarding claim 8, Seo teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Seo further teaches, wherein the first region and the first gate pattern correspond to one of the first and second isolation transistors, and the first gate pattern is configured to receive the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0110).
Regarding claim 9, Seo teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Seo further teaches, wherein the second region and the second gate pattern correspond to one of the first and second equalizing transistors, and the second gate pattern is configured to receive the equalizing signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0114).
Regarding claim 10, Seo teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Seo further teaches, wherein the second region and the third gate pattern correspond to one of the first and second offset cancellation transistors, and the third gate pattern is configured to receive the offset cancellation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121).
Regarding claim 11, Seo teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Seo further teaches, wherein the second active region and the fourth gate pattern correspond to one of the first and second NMOS transistors, and wherein the third active region and the fifth gate pattern correspond to one of the first and second PMOS transistors (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0109).
Regarding claim 12, Seo teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Seo further teaches, wherein each of the first active region and the second active region is N-type and the third active region is P-type (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058).
Regarding claim 13, Seo teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Seo further teaches, wherein the P-type amplifier is connected to: a first supply line at a first node at which the first control signal is applied, the bit-line at a third node, and the complementary bit-line at a fourth node, , and wherein the N-type amplifier is connected to: a second supply line at a second node at which the second control signal is applied, the sensing bit-line at a fifth node, and the complementary sensing bit-line at a sixth node (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0110).
Regarding claim 14, Seo teaches all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Seo further teaches, wherein, during a precharge period: the equalizer is configured to provide the precharge voltage to the sensing bit-line and the complementary sensing bit-line, based on the equalizing signal, the offset cancellation circuit is configured to connect the fifth node to the fourth node, and connect the sixth node to the third node, based on the offset cancellation signal, and the isolation circuit is configured to connect the fifth node to the third node, and connect the sixth node to the fourth node, based on the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0115).
Regarding claim 15, Seo teaches all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Seo further teaches, wherein, during an offset cancellation period: the equalizer is configured to disconnect a first precharge voltage node at which the precharge voltage is applied from the sensing bit-line and disconnect a second precharge voltage node at which the precharge voltage is applied from the complementary sensing bit-line, based on the equalizing signal, the offset cancellation circuit is configured to connect the fifth node to the fourth node, and connect the sixth node to the third node, based on the offset cancellation signal, and the isolation circuit is configured to disconnect the fifth node from the third node, and disconnect the sixth node from the fourth node, based on the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-7).
Regarding claim 16, Seo teaches all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Seo further teaches, wherein, during a charge sharing period: the equalizer is configured to provide the precharge voltage to the sensing bit-line and the complementary sensing bit-line, based on the equalizing signal, the offset cancellation circuit is configured to disconnect the fifth node from the fourth node, and disconnect the sixth node to the third node, based on the offset cancellation signal, and the isolation circuit is configured to disconnect the fifth node from the third node, and disconnect the sixth node from the fourth node, based on the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0115).
Regarding claim 17, Seo teaches all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Seo further teaches, wherein, during a shifting period, the equalizer is configured to disconnect a first precharge voltage node at which the precharge voltage is applied from the sensing bit-line and disconnect a second precharge voltage node at which the precharge voltage is applied from the complementary sensing bit-line, based on the equalizing signal, the offset cancellation circuit is configured to disconnect the fifth node from the fourth node, and disconnect the sixth node from the third node, based on the offset cancellation signal, and the isolation circuit is configured to connect the fifth node to the third node, and connect the sixth node to the fourth node, based on the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0110).
Regarding independent claim 18, Seo teaches a semiconductor memory device comprising: a first memory cell connected to a first word-line and a bit-line; a second memory cell connected to a second word-line and a complementary bit-line (see Fig. 1-3, 17-21 and paragraph 0045-0058, 01080121, claim 1-11 where left and right memory cell MC are first and second memory cell coupled to first wordline WL, first bitline BL and second wordline WL, second bitline BLB accordingly); a bit-line sense amplifier connected to the bit-line and the complementary bit-line, and the bit-line sense amplifier configured to: sense a voltage difference between the bit-line and the complementary bit-line, and amplify the voltage difference; and a timing control circuit configured to control an operation of the bit-line sense amplifier based on internal command signals, wherein the bit-line sense amplifier comprises: an amplifying circuit including a P-type amplifier connected to the bit-line and the complementary bit-line and an N-type amplifier connected to a sensing bit-line and a complementary sensing bit-line (see Fig. 1-3, 17-21 and paragraph 0045-0058, 0108-0121, claim 1-11 where unit 353p, 353n are P-type amplifier, N-type amplifier accordingly), the amplifying circuit configured to: sense the voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjust a voltage of the sensing bit-line and the complementary sensing bit-line based on the voltage difference (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, Pre-sensing operation includes amplifying / reducing voltage level based on sensing voltage variation-see specially paragraph 0008); an offset cancellation circuit configured to connect the bit-line and the complementary bit-line to the complementary sensing bit-line and the sensing bit-line, respectively, based on an offset cancellation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, offset cancellation circuit OC_1, OC_2, OC is offset cancellation signal); an equalizer configured to provide a precharge voltage to the sensing bit-line and the complementary sensing bit-line based on an equalizing signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11 where E_1, E_2, E_3 are equalizer); and an isolation circuit connected between the bit-line and the sensing bit-line and between the complementary bit-line and the complementary sensing bit-line, and the isolation circuit configured to: connect the sensing bit-line and the complementary sensing bit-line equalized with the precharge voltage to the bit-line and the complementary bit-line, respectively, based on an isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, Isolation circuits ISO_1, ISO_2 which connect sensing bitline BL and complementary bit-line BLB, ISO is isolation signal).
Even though Seo teach Pre-sensing operation but silent exclusively about adjust a voltage of the sensing bit-line and the complementary sensing bit-line. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Seo where pre-sensing operation which includes amplifying / reducing voltage level i.e. adjusting voltage level based on sensing voltage variation (see specially paragraph 0008, last 3 lines) in order to have sense amplifier with improved area, sensing margin and reduced cost of memory device (see paragraph 0106, 0133).
Regarding claim 19, Seo teaches all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Seo further teaches, wherein the P-type amplifier includes: a first p-channel metal-oxide semiconductor (PMOS) transistor connected to a first supply line at a first node at which the first control signal is applied and connected to the bit-line at a third node, and including a gate connected to the complementary bit-line at a fourth node, and a second PMOS transistor connected between the first supply line and the fourth node, and including a gate connected to the third node, wherein the N-type amplifier includes: a first n-channel metal-oxide semiconductor (NMOS) transistor connected to a second supply line at a second node at which the second control signal is applied and connected to the sensing bit-line at a fifth node (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0110), and including a gate connected to the fourth node, and a second NMOS transistor connected to the second supply line at the second node and connected to the complementary sensing bit-line at a sixth node, and including a gate connected to the third node, wherein the equalizer includes: a first equalizing transistor connected between a first precharge voltage node at which the precharge voltage is applied and the fifth node, and including a gate configured to receive the equalizing signal, and a second equalizing transistor connected between a second precharge voltage node at which the precharge voltage is applied and the fifth node (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-5), and including a gate configured to receive the equalizing signal, and wherein the isolation circuit includes: a first isolation transistor connected between the third node and the fifth node, and including a gate configured to receive the isolation signal, and a second isolation transistor connected between the fourth node and the sixth node, and including a gate configured to receive the isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121).
Regarding independent claim 20, Seo teaches a semiconductor memory device comprising: a first memory cell connected to a first word-line and a bit-line; a second memory cell connected to a second word-line and a complementary bit-line (see Fig. 1-3, 17-21 and paragraph 0045-0058, 01080121, claim 1-11 where left and right memory cell MC are first and second memory cell coupled to first wordline WL, first bitline BL and second wordline WL, second bitline BLB accordingly); a bit-line sense amplifier connected to the bit-line and the complementary bit-line, and the bit-line sense amplifier comprising: an amplifying circuit including a P-type amplifier connected to the bit-line and the complementary bit-line and an N-type amplifier connected to a sensing bit-line and a complementary sensing bit-line (see Fig. 1-3, 17-21 and paragraph 0045-0058, 0108-0121, claim 1-11 where unit 353p, 353n are P-type amplifier, N-type amplifier accordingly), and the amplifying circuit configured to: sense a voltage difference between the bit-line and the complementary bit-line based on a first control signal and a second control signal, and adjust a voltage of the sensing bit-line and the complementary sensing bit-line based on the voltage difference (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, Pre-sensing operation includes amplifying / reducing voltage level based on sensing voltage variation-see specially paragraph 0008); an offset cancellation circuit configured to connect the bit-line and the complementary bit-line to the complementary sensing bit-line and the sensing bit-line, respectively, based on an offset cancellation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, offset cancellation circuit OC_1, OC_2, OC is offset cancellation signal); an equalizer configured to provide a precharge voltage to the sensing bit-line and the complementary sensing bit-line based on an equalizing signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11 where E_1, E_2, E_3 are equalizer); and an isolation circuit connected between the bit-line and the sensing bit-line and between the complementary bit-line and the complementary sensing bit-line, and the isolation circuit configured to: connect the sensing bit-line and the complementary sensing bit-line equalized with the precharge voltage to the bit-line and the complementary bit-line, respectively, based on an isolation signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11, Isolation circuits ISO_1, ISO_2 which connect sensing bitline BL and complementary bit-line BLB, ISO is isolation signal), wherein the P-type amplifier is connected to: a first supply line at a first node at which the first control signal is applied, the bit-line at a third node, and the complementary bit-line at a fourth node, wherein the N-type amplifier is connected to: a second supply line at a second node at which the second control signal is applied, the sensing bit-line at a fifth node, and the complementary sensing bit-line at a sixth node (see Fig. 1-3, 17-21 and paragraph 0045-0058, 0108-0121, claim 1-11 where unit 353p, 353n are P-type amplifier, N-type amplifier accordingly3), wherein the equalizer comprises: a first equalizing transistor connected between a first precharge voltage node at which the precharge voltage is applied and the fifth node, and including a gate configured to receive the equalizing signal; and a second equalizing transistor connected between a second precharge voltage node at which the precharge voltage is applied and the sixth node, and including a gate configured to receive the equalizing signal, and wherein the isolation circuit comprises: a first isolation transistor connected between the third node and the fifth node, and including a gate configured to receive the isolation signal; and a second isolation transistor connected between the fourth node and the sixth node, and including a gate configured to receive the isolation signal signal (see Fig. 1-3, 17-21 and paragraph 0007-0008, 0045-0058, 0108-0121, claim 1-11 where E_1, E_2, E_3 are equalizer transistors and PEQ is equalizing signal).
Even though Seo teach Pre-sensing operation but silent exclusively about adjust a voltage of the sensing bit-line and the complementary sensing bit-line. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Seo where pre-sensing operation which includes amplifying / reducing voltage level i.e. adjusting voltage level based on sensing voltage variation (see specially paragraph 0008, last 3 lines) in order to have sense amplifier with improved area, sensing margin and reduced cost of memory device (see paragraph 0106, 0133).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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