DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17 – 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II (method claims), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/15/2026.
Allowable Subject Matter
Claims 4, 10, 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 states “located on the negative main surface of the insulator layer located farther in the negative direction”. This would seem to be missing “first” and may be written as “located on the negative main surface of the first insulator layer located farther in the negative direction”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6, 8, 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hayashi (US 2013/0153279 A1; herein referenced as “Hayashi’279”).
Regarding Claim 1, Hayashi’279 (US 2013/0153279 A1) discloses a circuit board (Fig 1-5) comprising: a multilayer body (3) including a plurality of insulator layers (13,14) including a first insulator layer (13) and a second insulator layer (14), the second insulator layer (14) having a Young's modulus ([0031] “Moreover, being lower in Young's modulus than the inorganic insulating layer 14 and prone to elastic deformation, the resin layer 13 allows, when the wiring board 3 is subjected to stress, reduction of the stress applied to the inorganic insulating layer 14 and thus suppression of cracking that occurs in the inorganic insulating layer 14 due to the stress”) at room temperature ([0033] “ISO 14577-1: 2002”; see ISO-14577-1-2002.pdf) higher than a Young's modulus ([0031]) at room temperature of the first insulator layer (13), the first and second insulator layers (13,14) being laminated in a Z-axis direction (see Fig 1), the plurality of insulator layers (13,14) each including a negative main surface (lower surface of 13,14) located in a negative direction of a Z-axis and a positive main surface (upper surface of 13,14) located in a positive direction of the Z-axis, the negative main surface of the second insulator layer (14) being in contact with (lower surface of 14 contacts upper surface of 13) the positive main surface of the first insulator layer (13); an interlayer connection conductor (12; [0055-0056]) provided inside a through-hole (V) that passes through the first insulator layer (13) and the second insulator layer (14) in the Z-axis direction; a first conductor layer (11) that is located on the negative main surface of the insulator layer (10,13) located farther in the negative direction of the Z-axis than the second insulator layer (14), and that is in contact ([0029]) with an end portion of the interlayer connection conductor (12) in the negative direction of the Z-axis; and a second conductor layer (11) that is located on the positive main surface of the second insulator layer (14) and that is in contact with an end portion of the interlayer connection conductor (12) in the positive direction of the Z-axis; wherein a surface roughness ([0060]) of a portion (portion or region about V1) located in the second insulator layer (14) within an inner peripheral surface (surface of V1 at 14) of the through-hole (V) is larger than ([0060] “It is preferable that the ten-point average roughness of the inner wall of the first penetrating portion V1 is higher than the ten-point average roughness of the inner wall of the via-hole V existing in the resin layer 13, or more specifically the inner wall of the second penetrating portion V2”) a surface roughness of a portion (portion or region of V2 at 13) located in the first insulator layer (13) within the inner peripheral surface of the through-hole (V); and no conductor layer (no 11 is shown between 13 and 14 in Fig 1) in contact with the interlayer connection conductor is provided between the first insulator layer (13) and the second insulator layer (14).
Regarding Claim 2, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 1, wherein the first conductor layer (11) is located on the negative main surface (11 is shown on lower surface of 13 in Fig 1) of the first insulator layer (13).
Regarding Claim 5, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 1, wherein no conductor layer (no 11 is shown between 13 and 14 in Fig 1) is provided between the first insulator layer (13) and the second insulator layer (14).
Regarding Claim 6, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 1, wherein the interlayer connection conductor (12) does not pass through the first conductor layer (11) and the second conductor layer (11) in the Z-axis direction.
Regarding Claim 8, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 1, wherein the second insulator layer (14) has a structure in which a plurality of particles (14a,14b) are dispersed in a resin ([0043]).
Regarding Claim 9, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 8, wherein the plurality of particles (14) each have a shape ([0045,0051,0055,0062,0064]) having a longitudinal direction and a transverse direction (a spherical shape would extend in a longitudinal and a transverse direction).
Regarding Claim 11, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 8, wherein a portion of the plurality of particles (14b) is exposed on the inner peripheral surface (surface at V1) of the through-hole (V) of the second insulator layer (14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 2013/0153279 A1; herein referenced as “Hayashi’279”) as applied to claim 1 above, and further in view of Stahr (US 10,356,904 B2).
Regarding Claim 3, Hayashi’279 further discloses the circuit board (Fig 1-5) according to claim 1, wherein the plurality of insulator layers include a third insulator layer (lower 14 in Fig 1); the third insulator layer (lower 14) has a Young's modulus ([0031]) at room temperature ([0033]) higher than the Young's modulus at room temperature of the first insulator layer (13), and is located farther in the negative direction of the Z-axis than the first insulator layer (lower 14 is on a lower surface of uppermost 13 in Fig 1), and is in contact with the first insulator layer (13); and the insulator layer located farther in the negative direction of the Z-axis than the second insulator layer (uppermost 14 in Fig 1) is the third insulator layer (lower 14 in Fig 1).
Hayashi’279 does not disclose the through-hole passes through the third insulator layer in the Z-axis direction.
Stahr (US 10,356,904 B2) teaches of a circuit board (Fig 4) wherein a through-hole (Column 4, lines 6-18) passes through a third insulator layer (102) in the Z-axis direction.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Hayashi’279, wherein the through-hole passes through the third insulator layer in the Z-axis direction as taught by Stahr, in order to transmit electric signals and allow operation of an electronic device with electrical connections through a support structure (Column 3, lines 30-50) and furthermore since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art in order to transmit electric signals and allow operation of an electronic device with electrical connections through a support structure. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 2013/0153279 A1; herein referenced as “Hayashi’279”) as applied to claim 1 above, and further in view of Sakai (US 2014/0209356 A1).
Regarding Claim 7, Hayashi’279 discloses the limitations of the preceding claim.
Hayashi’279 does not disclose the circuit board according to claim 1, wherein when viewed in the Z-axis direction, an area of an end of the interlayer connection conductor in the positive direction of the Z-axis is smaller than an area of an end of the interlayer connection conductor in the negative direction of the Z-axis.
Sakai (US 2014/0209356 A1) teaches of a circuit board (Fig 8) wherein when viewed in the Z-axis direction (though this view is not shown, all views would meet this structural limitation as seen in Fig 8), an area ([0095-0097] vias shown have diameter) of an end of an interlayer connection conductor (15) in a positive direction (upward in Fig 8) of the Z-axis is smaller than an area ([0095-0097] vias shown have diameter) of an end of the interlayer connection conductor (15) in the negative direction of the Z-axis (vias taper such that the diameter is greater towards the lower end of Fig 8).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Hayashi’279, wherein when viewed in the Z-axis direction, an area of an end of the interlayer connection conductor in the positive direction of the Z-axis is smaller than an area of an end of the interlayer connection conductor in the negative direction of the Z-axis as taught by Sakai, in order to provide high frequency characteristics, to permit distance between lower wirings to be increased and allow distances between upper wirings or at a mounting surface to reduce (Sakai, [0096,0104-0114]).
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 2013/0153279 A1; herein referenced as “Hayashi’279”) as applied to claim 1 above, and further in view of Nakamura (US 2016/0133555 A1).
Regarding Claim 12, Hayashi’279 discloses the limitations of the preceding claim.
Hayashi’279 does not disclose the circuit board according to claim 1, wherein a surface roughness of a positive main surface of the first conductor layer is smaller than a surface roughness of a negative main surface of the first conductor layer, and a surface roughness of a negative main surface of the second conductor layer is larger than a surface roughness of a positive main surface of the second conductor layer.
Nakamura (US 2016/0133555 A1) teaches of a circuit board (Fig 1-2) wherein a surface roughness ([0027,0033,0034,0036,0037]) of a positive main surface (upper surface) of a first conductor layer (32) is smaller than (see Fig 2) a surface roughness ([0027,0033,0036,0037]) of a negative main surface (lower surface of 2) of the first conductor layer (32), and a surface roughness ([0027,0033,0034,0036,0037]) of a negative main surface of a second conductor layer (34) is larger than (see Fig 2) a surface roughness ([0027,0033,0036,0037]) of a positive main surface of the second conductor layer (34).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Hayashi’279, wherein a surface roughness of a positive main surface of the first conductor layer is smaller than a surface roughness of a negative main surface of the first conductor layer, and a surface roughness of a negative main surface of the second conductor layer is larger than a surface roughness of a positive main surface of the second conductor layer as taught by Nakamura, in order to provide strong adhesion, improve bonding of a via, provide stable electrical characteristics, prevent peeling, prevent crack generation, and improve reliability (Nakamura, [0027-0037,0045,0063-0067]).
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 2013/0153279 A1; herein referenced as “Hayashi’279”) as applied to claim 1 above, and further in view of Tuominen (US 2021/0045235 A1).
Regarding Claim 15, Hayashi’279 discloses the limitations of the preceding claim.
Hayashi’279 does not disclose the circuit board according to claim 1, wherein the multilayer body includes a first section and a second section, and the second section is bent, relative to the first section, in the Z-axis direction of the first section.
Tuominen (US 2021/0045235 A1) teaches of a circuit board (Fig 1-7) wherein a multilayer body (102) includes a first section (108) and a second section (108,110), and the second section (108,110) is bent, relative to the first section (108), in the Z-axis direction of the first section (108).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Hayashi’279, wherein the multilayer body includes a first section and a second section, and the second section is bent, relative to the first section, in the Z-axis direction of the first section as taught by Tuominen, in order to increase functionalities, compensate for miniaturization, compensate for increasing number of components to be mounted, provide means of handling plurality of contacts with small spacing, provide mechanical robustness, prevent failure, and allow bending to install (Tuominen, [0003-0005,0015,0033-0039,0065]).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 2013/0153279 A1; herein referenced as “Hayashi’279”) as applied to claim 1 above, and further in view of Hayashi (US 2013/0043067 A1; herein referenced as “Hayashi’067”).
Regarding Claim 16, Hayashi’279 discloses the limitations of the preceding claim.
Hayashi’279 does not disclose the circuit board according to claim 1, wherein a thickness of the second insulator layer in the Z-axis direction is smaller than a thickness of the first insulator layer in the Z-axis direction.
Hayashi’067 (US 2013/0043067 A1) teaches of a circuit board (Fig 1-2A) wherein a thickness ([0026,0037]) of a second insulator layer (11a) in the Z-axis direction is smaller than a thickness ([0026,0037]) of a first insulator layer (10a) in the Z-axis direction.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Hayashi’279, wherein a thickness of the second insulator layer in the Z-axis direction is smaller than a thickness of the first insulator layer in the Z-axis direction as taught by Hayashi’067, in order to provide reliability, reduce disconnections, suppress separation, prevent short-circuiting and control rigidity (Hayashi’067, [0005,0026-0037,0049,0059]). The combination would also allow control of the overall thickness of the circuit board which would then provide functionality of the space intended for the circuit board to be placed within.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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