DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/8/2024, 9/5/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 3 is objected to because of the following informalities:
In claim 3, line 2, the limitation of “differ” should be corrected int “differs”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10-11 and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsui (US 2015/0279792).
Regarding claim 1, Matsui discloses, in at least figure 2 and related text, a semiconductor device comprising:
a semiconductor chip (201, [30]) in which a plurality of terminal groups (203/204/205, [30]) including a plurality of terminals (203a/204a of 203/204, [32], [33]) disposed along a first direction (horizontal direction, figure) are disposed along a second direction (vertical direction, figure) that intersects the first direction (horizontal direction, figure),
wherein at least one of the plurality of terminal groups (204, [30]) includes a first terminal (204a in 204c adjacent to right end 204a in 204c, figure), a second terminal (right end 204a in 204c, figure) adjacent to the first terminal (204a in 204c adjacent to right end 204a in 204c, figure) in the first direction (horizontal direction, figure), a third terminal (left end 204a in 204d, figure) adjacent to the second terminal (right end 204a in 204c, figure) on an opposite side thereof from the first terminal (204a in 204c adjacent to right end 204a in 204c, figure) in the first direction (horizontal direction, figure), and a fourth terminal (204a in 204d adjacent to left end 204a in 204d, figure) adjacent to the third terminal (left end 204a in 204d, figure) on an opposite side thereof from the second terminal (right end 204a in 204c, figure) in the first direction (horizontal direction, figure);
a spacing between the first terminal (204a in 204c adjacent to right end 204a in 204c, figure) and the second terminal (right end 204a in 204c, figure) in the first direction (horizontal direction, figure) is wider than a spacing between the second terminal (right end 204a in 204c, figure) and the third terminal (left end 204a in 204d, figure) in the first direction (horizontal direction, figure); and
the spacing between the second terminal (right end 204a in 204c, figure) and the third terminal (left end 204a in 204d, figure) in the first direction (horizontal direction, figure) is wider than a spacing between the third terminal (left end 204a in 204d, figure) and the fourth terminal (204a in 204d adjacent to left end 204a in 204d, figure) in the first direction (horizontal direction, figure).
Regarding claim 10, Matsui discloses the semiconductor device according to claim 1 as described above.
Matsui further discloses, in at least figure 2 and related text, in at least one of the plurality of terminal groups (204, [30]), a spacing between two terminals (204a, [33]) adjacent to each other in the first direction widens gradually with increasing proximity to the center of the terminal group in the first direction (horizontal direction, figure).
Regarding claim 11, Matsui discloses the semiconductor device according to claim 1 as described above.
Matsui further discloses, in at least figure 2 and related text, the first direction (horizontal direction, figure) is a row direction and the second direction (vertical direction, figure) is a column direction.
Regarding claim 14, Matsui discloses the semiconductor device according to claim 1 as described above.
The claimed limitation of "A display device comprising: a display unit having the semiconductor device according to claim 1; and a control circuit configured to control the display unit" has not patentable weight because it is interpreted as intended use.
Regarding claim 15, Matsui discloses the semiconductor device according to claim 1 as described above.
The claimed limitation of "A photoelectric conversion device comprising: an optical unit; an imaging element configured to receive light that has passed through the optical unit; and a display unit configured to display an image captured by the imaging element, wherein the display unit has the semiconductor device according to claim 1" has not patentable weight because it is interpreted as intended use.
Regarding claim 16, Matsui discloses the semiconductor device according to claim 1 as described above.
The claimed limitation of "An electronic device comprising: a display unit having the semiconductor device according to claim 1; a housing in which the display unit is provided; and a communication unit that is provided in the housing and that communicates with the exterior" has not patentable weight because it is interpreted as intended use.
Claim(s) 2-4 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon (US 2005/0162577).
Regarding claim 2, Yoon discloses, in at least figure 5 and related text, a semiconductor device comprising:
a semiconductor chip (300, [50]) in which a plurality of terminal groups (DT1-1 to DT2-d/DT2-1 to D1-a, [51]) including a plurality of terminals disposed along a first direction (horizontal direction, figure) are disposed along a second direction (vertical direction, figure) that intersects the first direction (horizontal direction, figure),
wherein the plurality of terminal groups (DT1-1 to DT2-d/DT2-1 to D1-a, [51]) includes a first terminal group (DT1-1 to DT2-d, [51]) and a second terminal group (DT2-1 to D1-a, [51]);
a spacing between a central portion of the first terminal group (DT1-1 to DT2-d, [51]) in the first direction (horizontal direction, figure) and a central portion of the second terminal group in the first direction (horizontal direction, figure) is narrower than a spacing between an intermediate portion disposed between the central portion and an end portion of the first terminal group (DT1-1 to DT2-d, [51]) in the first direction (horizontal direction, figure), and an intermediate portion disposed between the central portion and an end portion of the second terminal group (DT2-1 to D1-a, [51]) in the first direction (horizontal direction, figure); and
a spacing between the intermediate portion of the first terminal group (DT1-1 to DT2-d, [51]) in the first direction (horizontal direction, figure) and the intermediate portion of the second terminal group (DT2-1 to D1-a, [51]) in the first direction (horizontal direction, figure) is narrower than a spacing between the end portion of the first terminal group (DT1-1 to DT2-d, [51]) in the first direction (horizontal direction, figure) and the end portion of the second terminal group (DT2-1 to D1-a, [51]) in the first direction (horizontal direction, figure).
Regarding claim 3, Yoon discloses the semiconductor device according to claim 2 as described above.
Yoon further discloses, in at least figure 5 and related text, a position of the terminal in the second direction (vertical direction, figure) differ between the central portion of the first terminal group (DT1-1 to DT2-d, [51]) and the end portion of the first terminal group (DT1-1 to DT2-d, [51]).
Regarding claim 4, Yoon discloses the semiconductor device according to claim 3 as described above.
Yoon further discloses, in at least figure 5 and related text, a position of the terminal in the second direction (vertical direction, figure) differs between the central portion of the second terminal group (DT2-1 to D1-a, [51]) and the end portion of the second terminal group (DT2-1 to D1-a, [51]).
Regarding claim 7, Yoon discloses the semiconductor device according to claim 2 as described above.
Yoon further discloses, in at least figure 5 and related text, a spacing between the first terminal group (DT1-1 to DT2-d, [51]) and the second terminal group (DT2-1 to D1-a, [51]) narrows down gradually with increasing proximity to a center of the first terminal group (DT1-1 to DT2-d, [51]) in the first direction (horizontal direction, figure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon (US 2005/0162577) in view of Matsui (US 2015/0279792).
Regarding claim 8, Yoon discloses the semiconductor device according to claim 2 as described above.
Yoon does not explicitly disclose one of the first terminal group and the second terminal group is an input terminal group, and the other of the first terminal group and the second terminal group is an output terminal group.
Matsui teaches, in at least figure 2 and related text, the device comprising one of the first terminal group (203, [32]) and the second terminal group (204, [32]) is an input terminal group, and the other of the first terminal group (203, [32]) and the second terminal group (204, [32]) is an output terminal group, for the purpose of providing a drive chip that makes it possible to secure a sufficient area for circuitry and simultaneously to prevent defective connection by suppressing a warp ([7]).
Yoon and Matsui are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon with the specified features of Matsui because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Yoon to have one of the first terminal group and the second terminal group being an input terminal group, and the other of the first terminal group and the second terminal group being an output terminal group, as taught by Matsui, for the purpose of providing a drive chip that makes it possible to secure a sufficient area for circuitry and simultaneously to prevent defective connection by suppressing a warp ([7], Matsui).
Regarding claim 9, Yoon discloses the semiconductor device according to claim 2 as described above.
Yoon does not explicitly disclose at least one of the plurality of terminal groups includes a first terminal, a second terminal adjacent to the first terminal in the first direction, and a third terminal adjacent to the second terminal on an opposite side thereof from the first terminal in the first direction, and a spacing between the first terminal and the second terminal in the first direction is wider than a spacing between the second terminal and the third terminal in the first direction.
Matsui teaches, in at least figure 2 and related text, the device comprising at least one of the plurality of terminal groups (204, [30]) includes a first terminal (204a in 204c adjacent to right end 204a in 204c, figure), a second terminal (right end 204a in 204c, figure) adjacent to the first terminal (204a in 204c adjacent to right end 204a in 204c, figure) in the first direction (horizontal direction, figure), a third terminal (left end 204a in 204d, figure) adjacent to the second terminal (right end 204a in 204c, figure) on an opposite side thereof from the first terminal (204a in 204c adjacent to right end 204a in 204c, figure) in the first direction (horizontal direction, figure), and a spacing between the first terminal (204a in 204c adjacent to right end 204a in 204c, figure) and the second terminal (right end 204a in 204c, figure) in the first direction (horizontal direction, figure) is wider than a spacing between the second terminal (right end 204a in 204c, figure) and the third terminal (left end 204a in 204d, figure) in the first direction (horizontal direction, figure), for the purpose of providing a drive chip that makes it possible to secure a sufficient area for circuitry and simultaneously to prevent defective connection by suppressing a warp ([7]).
Yoon and Matsui are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoon with the specified features of Matsui because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Yoon to have the at least one of the plurality of terminal groups including a first terminal, a second terminal adjacent to the first terminal in the first direction, and a third terminal adjacent to the second terminal on an opposite side thereof from the first terminal in the first direction, and the spacing between the first terminal and the second terminal in the first direction being wider than a spacing between the second terminal and the third terminal in the first direction, as taught by Matsui, for the purpose of providing a drive chip that makes it possible to secure a sufficient area for circuitry and simultaneously to prevent defective connection by suppressing a warp ([7], Matsui).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsui (US 2015/0279792) in view of Yoon (US 2005/0162577).
Regarding claim 12, Matsui discloses the semiconductor device according to claim 1 as described above.
Matsui does not explicitly disclose a semiconductor substrate provided with a plurality of electrodes connected respectively, via a connection member, to the plurality of terminals of the semiconductor chip.
Yoon teaches, in at least figures 9-11 and related text, the device comprising a semiconductor substrate (810, [75]) provided with a plurality of electrodes (812, [75]) connected respectively, via a connection member (900, [86]), to the plurality of terminals ([78]) of the semiconductor chip (100, [73]), for the purpose of providing a driver chip capable of enhancing a reliability of connection between the driver chip and a display panel ([12]).
Matsui and Yoon are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Matsui with the specified features of Yoon because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Matsui to have the semiconductor substrate provided with a plurality of electrodes connected respectively, via a connection member, to the plurality of terminals of the semiconductor chip, as taught by Yoon, for the purpose of providing a driver chip capable of enhancing a reliability of connection between the driver chip and a display panel ([12], Yoon).
Regarding claim 13, Matsui in view of Yoon discloses the semiconductor device according to claim 12 as described above.
Yoon further teaches, in at least figures 9-11 and related text, the plurality of terminals ([78]) of the semiconductor chip (100, [73]) and the plurality of electrodes (812, [75]) of the semiconductor substrate (810, [75]) are connected to each other by thermocompression bonding or ultrasonic compression joining using an epoxy resin, an acrylic resin or an anisotropic conductive resin ([86], [87]) as the connection member (900, [86]), for the purpose of providing a driver chip capable of enhancing a reliability of connection between the driver chip and a display panel ([12]).
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 2 and 5 that recite "a size of the terminal in the second direction at the central portion of the first terminal group is larger than a size of the terminal in the second direction at the end portion of the first terminal group" in combination with other elements of the base claims 2 and 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONG-HO KIM/ Primary Examiner, Art Unit 2811
Prosecution Insights