DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 3, 10, and 11 are objected to because of the following informalities:
Regarding claim 3, it states “… the pair of word lines entirely overlapping the third portion …”. It should read “… the pair of word lines entirely overlap appropriate correction is required.
Regarding claim 10, it states “… first direction being parallel to the upper surface the substrate …”. It should read “… first direction being parallel to the upper surface of the substrate …”, or another appropriate correction is required.
Regarding claim 11, it states “… the third portion is between facing surfaces …”. It should read “… the third portion is between the facing surfaces …”, or another appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, it recites the limitation "… the bit line than the surfaces of the word lines facing each other in the vertical direction" in lines 3 and 4 of the claim. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “… the bit line than the facing surfaces of the pair of word lines are in the vertical direction.”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Allowable Subject Matter
Claims 1-11 and 13-20 are allowed.
Claim 12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor renders obvious the following limitations when taken in combination with all other limitations:
wherein each of the semiconductor patterns include
a first portion connected to the bit line and including polysilicon,
a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and
a third portion between the first portion and the second portion and including a metal silicide material. (Applicant fig 2, ¶0048-0050).
Cho et al (US 20220285353 A1, hereafter Cho) teaches: A semiconductor device (Cho 100, fig 4A, 4B, 9G) comprising:
a substrate (Cho PERI, ¶0064);
a bit line (Cho BL, ¶0026) extending in a vertical direction (Cho D1)(Cho fig 4A, 4B, ¶0026), the vertical direction being perpendicular to an upper surface of the substrate (Cho fig 4A, 4B);
semiconductor patterns (Cho ACT/13, SR/21, CH/13, DR/25, ¶0028-0029, 0059, 0075) having first ends (Cho E1, ¶0029, 0088) connected to the bit line (Cho fig 4B, 9G, ¶0029) and spaced apart in the vertical direction (Cho fig 4B, ¶0059, multiple ACT, SR, CH, DR spaced vertically from each other);
a pair of word lines (Cho DWL, WL1, WL2, ¶0027, 0034, 0059) above and below respective semiconductor patterns (Cho fig 4B, 9G, ¶0059 multiple DWL shown, each having WL1 and WL2, wherein WL1 and WL2 are respectively above and below a singular ACT); and
data storage patterns (Cho CAP, SN, DE, PN, ¶0025, 0047, under a broadest reasonable interpretation of “data storage patterns”, CAP contains “storage node SN”) connected to second ends (Cho E2, ¶0029, 0093) of respective semiconductor patterns (Cho fig 4B, 9G, ¶0029),
wherein each of the semiconductor patterns (Cho ACT/13, SR/21, CH/13, DR/25) include
a first portion (Cho SR/21, ¶0029, 0088) connected to the bit line (Cho fig 4B, 9G, ¶0029) and including polysilicon (Cho ¶0028, 0075, 0088, fig 9A, 9B, formed by doping polysilicon layer 13),
a second portion (Cho DR/25, ¶0029, 0093) connected to each of the data storage patterns (Cho fig 4B, 9G, ¶0029), and
a third portion (Cho CH/13, ¶0029, 0075, 0092) between the first portion and the second portion (Cho fig 4B, 9E, ¶0028-0029).
However, Cho’s active layer is a single semiconductor material, either silicon or IGZO as whole layer alternatives (Cho ¶0028), and Cho’s silicides are terminal ohmic contact in contact with either the first portion or the second portions (Cho BOC/22, ¶0037, SOC/26, ¶0048).
Song et al (US 20230157021 A1, as disclosed in IDS dated 07/08/2024, hereafter Song) teaches: a first portion including polysilicon (Song 1111-1, fig 11, ¶0126), and a second portion including an oxide semiconductor material (Song 1111-2, ¶0126), wherein the first portion and the second portion are a continuous channel layer (Song 1111, fig 13D-13F, ¶122).
However, Song’s portions join by an N-type junction doping (Song ¶0130) and contain no metal-silicide portion between its portions.
Verhulst (US 20080067495 A1, as disclosed in IDS dated 07/08/2024, hereafter Verhulst) teaches: a third portion (Verhulst 4, 9, fig 2, ¶0010, ¶0098) between a first portion (Verhulst 3, ¶0013, 0068) and a second portion (Verhulst 5, ¶0100)(Verhulst fig 2) and including a metal silicide material (Verhulst ¶0014, 0021, 0089).
However, Verhulst fails to disclose first and second portions having a different composition.
Neither Cho, Song, nor Verhulst, either alone or in combination, teaches: wherein each of the semiconductor patterns include a first portion connected to the bit line and including polysilicon, a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material, as required by claim 1.
Cho, Song, and Verhulst address different junctions than claimed, and one of ordinary skill in the art would have no reasonable expectation of success in combining them to arrive at the claimed semiconductor pattern. Therefore, Cho, Song, and Verhulst disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Cho, Song, Verhulst, or any other prior arts of record so that all of limitations of claim 1 as a whole can be met.
Regarding claims 2-9, the dependent claims are allowed for their dependency to claim 1.
Regarding claim 10, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor renders obvious the following limitations when taken in combination with all other limitations:
wherein each of the semiconductor patterns include
a first portion connected to the bit line and including polysilicon,
a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and
a third portion between the first portion and the second portion and including a metal silicide material. (Applicant fig 2, ¶0048-0050).
Cho et al (US 20220285353 A1, hereafter Cho) teaches: A semiconductor device (Cho 100, fig 4A, 4B, 9G) comprising:
a substrate (Cho PERI, ¶0064);
a bit line (Cho BL, ¶0026) extending in a vertical direction (Cho D1)(Cho fig 4A, 4B, ¶0026), the vertical direction being perpendicular to an upper surface of the substrate (Cho fig 4A, 4B);
semiconductor patterns (Cho ACT/13, SR/21, CH/13, DR/25, ¶0028-0029, 0059, 0075) having first ends (Cho E1, ¶0029, 0088) connected to the bit line (Cho fig 4B, 9G, ¶0029) and spaced apart in the vertical direction (Cho fig 4B, ¶0059, multiple ACT, SR, CH, DR spaced vertically from each other);
a pair of word lines (Cho DWL, WL1, WL2, ¶0027, 0034, 0059) above and below respective semiconductor patterns (Cho fig 4B, 9G, ¶0059 multiple DWL shown, each having WL1 and WL2, wherein WL1 and WL2 are respectively above and below a singular ACT) and extending in a first direction (Cho D3, ¶0025)(Cho fig 1, 4A, ¶0025), the first direction being parallel to the upper surface the substrate (as best understood to mean “the upper surface of the substrate”)(Cho fig 1, 4A); and
data storage patterns (Cho CAP, SN, DE, PN, ¶0025, 0047, under a broadest reasonable interpretation of “data storage patterns”, CAP contains “storage node SN”) connected to second ends (Cho E2, ¶0029, 0093) of respective semiconductor patterns (Cho fig 4B, 9G, ¶0029),
wherein each of the semiconductor patterns (Cho ACT/13, SR/21, CH/13, DR/25) include
a first portion (Cho SR/21, ¶0029, 0088) connected to the bit line (Cho fig 4B, 9G, ¶0029) and including polysilicon (Cho ¶0028, 0075, 0088, fig 9A, 9B, formed by doping polysilicon layer 13),
a second portion (Cho DR/25, ¶0029, 0093) connected to each of the data storage patterns (Cho fig 4B, 9G, ¶0029), and
a third portion (Cho CH/13, ¶0029, 0075, 0092) between the first portion and the second portion (Cho fig 4B, 9E, ¶0028-0029), and
an interface between the second portion and the third portion is between facing surfaces of the pair of word lines (surfaces of WL1 and WL2 as best shown by GD)(Cho fig 4B, 9E, an interface between CH and DR is vertically between inward facing surfaces of WL1 and WL2).
However, Cho’s active layer is a single semiconductor material, either silicon or IGZO as whole layer alternatives (Cho ¶0028), and Cho’s silicides are terminal ohmic contact in contact with either the first portion or the second portions (Cho BOC/22, ¶0037, SOC/26, ¶0048).
Song et al (US 20230157021 A1, as disclosed in IDS dated 07/08/2024, hereafter Song) teaches: a first portion including polysilicon (Song 1111-1, fig 11, ¶0126), and a second portion including an oxide semiconductor material (Song 1111-2, ¶0126), wherein the first portion and the second portion are a continuous channel layer (Song 1111, fig 13D-13F, ¶122).
However, Song’s portions join by an N-type junction doping (Song ¶0130) and contain no metal-silicide portion between its portions.
Verhulst (US 20080067495 A1, as disclosed in IDS dated 07/08/2024, hereafter Verhulst) teaches: a third portion (Verhulst 4, 9, fig 2, ¶0010, ¶0098) between a first portion (Verhulst 3, ¶0013, 0068) and a second portion (Verhulst 5, ¶0100)(Verhulst fig 2) and including a metal silicide material (Verhulst ¶0014, 0021, 0089).
However, Verhulst fails to disclose first and second portions having a different composition.
Neither Cho, Song, nor Verhulst, either alone or in combination, teaches: wherein each of the semiconductor patterns include a first portion connected to the bit line and including polysilicon, a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material, as required by claim 10.
Cho, Song, and Verhulst address different junctions than claimed, and one of ordinary skill in the art would have no reasonable expectation of success in combining them to arrive at the claimed semiconductor pattern. Therefore, Cho, Song, and Verhulst disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Cho, Song, Verhulst, or any other prior arts of record so that all of limitations of claim 10 as a whole can be met.
Regarding claims 11, 13, and 14, the dependent claims are allowed for their dependency to claim 10.
Regarding claim 15, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein each of the semiconductor patterns include
a first portion connected to the bit line and including polysilicon,
a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and
a third portion between the first portion and the second portion and including a metal silicide material. (Applicant fig 2, ¶0048-0050).
Cho et al (US 20220285353 A1, hereafter Cho) teaches: A semiconductor device (Cho 100, fig 4A, 4B, 9G) comprising:
a substrate (Cho PERI, ¶0064);
a bit line (Cho BL, ¶0026) extending in a vertical direction (Cho D1)(Cho fig 4A, 4B, ¶0026), the vertical direction being perpendicular to an upper surface of the substrate (Cho fig 4A, 4B);
semiconductor patterns (Cho ACT/13, SR/21, CH/13, DR/25, ¶0028-0029, 0059, 0075) having first ends (Cho E1, ¶0029, 0088) connected to the bit line (Cho fig 4B, 9G, ¶0029) and spaced apart in the vertical direction (Cho fig 4B, ¶0059, multiple ACT, SR, CH, DR spaced vertically from each other);
a pair of word lines (Cho DWL, WL1, WL2, ¶0027, 0034, 0059) above and below respective semiconductor patterns (Cho fig 4B, 9G, ¶0059 multiple DWL shown, each having WL1 and WL2, wherein WL1 and WL2 are respectively above and below a singular ACT) and extending in a first direction (Cho D3, ¶0025)(Cho fig 1, 4A, ¶0025) that is parallel to the upper surface the substrate (Cho fig 1, 4A); and
data storage patterns (Cho CAP, SN, DE, PN, ¶0025, 0047, under a broadest reasonable interpretation of “data storage patterns”, CAP contains “storage node SN”) connected to second ends (Cho E2, ¶0029, 0093) of respective semiconductor patterns (Cho fig 4B, 9G, ¶0029),
wherein each of the semiconductor patterns (Cho ACT/13, SR/21, CH/13, DR/25) include
a first portion (Cho SR/21, ¶0029, 0088) connected to the bit line (Cho fig 4B, 9G, ¶0029) and including polysilicon (Cho ¶0028, 0075, 0088, fig 9A, 9B, formed by doping polysilicon layer 13),
a second portion (Cho DR/25, ¶0029, 0093) connected to each of the data storage patterns (Cho fig 4B, 9G, ¶0029), and
a third portion (Cho CH/13, ¶0029, 0075, 0092) between the first portion and the second portion (Cho fig 4B, 9E, ¶0028-0029), and
the first portion, the third portion, and the second portion are sequentially arranged in a second direction (Cho D2, ¶0025) between the bit line and the data storage pattern (Cho fig 4B, 9G), the second direction being parallel to the upper surface of the substrate and perpendicular to the first direction (Cho fig 4A, 4B, 9E).
However, Cho’s active layer is a single semiconductor material, either silicon or IGZO as whole layer alternatives (Cho ¶0028), and Cho’s silicides are terminal ohmic contact in contact with either the first portion or the second portions (Cho BOC/22, ¶0037, SOC/26, ¶0048).
Song et al (US 20230157021 A1, as disclosed in IDS dated 07/08/2024, hereafter Song) teaches: a first portion including polysilicon (Song 1111-1, fig 11, ¶0126), and a second portion including an oxide semiconductor material (Song 1111-2, ¶0126), wherein the first portion and the second portion are a continuous channel layer (Song 1111, fig 13D-13F, ¶122).
However, Song’s portions join by an N-type junction doping (Song ¶0130) and contain no metal-silicide portion between its portions.
Verhulst (US 20080067495 A1, as disclosed in IDS dated 07/08/2024, hereafter Verhulst) teaches: a third portion (Verhulst 4, 9, fig 2, ¶0010, ¶0098) between a first portion (Verhulst 3, ¶0013, 0068) and a second portion (Verhulst 5, ¶0100)(Verhulst fig 2) and including a metal silicide material (Verhulst ¶0014, 0021, 0089).
However, Verhulst fails to disclose first and second portions having a different composition.
Neither Cho, Song, nor Verhulst, either alone or in combination, teaches: wherein each of the semiconductor patterns include a first portion connected to the bit line and including polysilicon, a second portion connected to each of the data storage patterns and including an oxide semiconductor material, and a third portion between the first portion and the second portion and including a metal silicide material, as required by claim 15.
Cho, Song, and Verhulst address different junctions than claimed, and one of ordinary skill in the art would have no reasonable expectation of success in combining them to arrive at the claimed semiconductor pattern. Therefore, Cho, Song, and Verhulst disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Cho, Song, Verhulst, or any other prior arts of record so that all of limitations of claim 15 as a whole can be met.
Regarding claims 16-20, the dependent claims are allowed for their dependency to claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shin et al (US 20230255015 A1) is cited as an example of an analogous device further disclosing an active region connected between a vertical bit line and a storage node between a pair of word lines above and below.
Hurkx et al (US 20090008631 A1) is cited as an example of an analogous device further disclosing a nanowire transistor with a silicide barrier between two silicon regions.
Avci et al (US 20170271501 A1) is cited as an example of an analogous device further disclosing a silicide nano wire with doped source and drain regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner
Art Unit 2818
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