DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,062,617. Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely seeks to broaden the claims by, for example, removing limitations requiring the redistribution via to have a tapered shape, and instead describing the vias as having greater maximum horizontal widths for the upper redistribution via than for the lower redistribution via. The scope of the claims are fully encompassed by US12062617, and the allowable subject matter still remains.
1. A semiconductor package comprising:
a first semiconductor chip including a first semiconductor substrate and a first chip pad, the first semiconductor substrate including a first bottom surface and a first top surface that is opposite to the first bottom surface, and the first chip pad being on the first bottom surface of the first semiconductor substrate
a second semiconductor chip including a second semiconductor substrate and a second chip pad, the second semiconductor substrate including a second bottom surface and a second top surface that is opposite to the second bottom surface, and the second chip pad being on the second top surface of the second semiconductor substrate
a lower redistribution structure provided on the first bottom surface of the first semiconductor chip and on the second bottom surface of the second semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern, the lower redistribution pattern including a lower redistribution via pattern contacting the first chip pad
a connection substrate on a top surface of the lower redistribution structure and including and a conductive connection structure and a substrate base having an accommodation space exposing the top surface of the lower redistribution structure and accommodating the first semiconductor chip and the second semiconductor chip therein, wherein the conductive connection structure passes through the substrate base
a molding layer covering the first semiconductor chip and the second semiconductor chip
an upper redistribution structure including an upper redistribution insulating layer and an upper redistribution pattern, the upper redistribution pattern including an upper redistribution line pattern and a first upper redistribution via pattern, the upper redistribution line pattern extending along a top surface of the molding layer, and the first upper redistribution via pattern extending from the top surface of the molding layer toward the second semiconductor chip and being connected to the second chip pad
a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern, wherein a horizontal width of the second chip pad is greater than a horizontal width of the first chip pad, and wherein a maximum horizontal width of the first upper redistribution via pattern is greater than a maximum horizontal width of the lower redistribution via pattern
1. A semiconductor package comprising:
a first semiconductor chip including a first semiconductor substrate and a first chip pad, the first semiconductor substrate including a first bottom surface and a first top surface that is opposite to the first bottom surface, and the first chip pad being on the first bottom surface of the first semiconductor substrate
a second semiconductor chip including a second semiconductor substrate and a second chip pad, the second semiconductor substrate including a second bottom surface and a second top surface that is opposite to the second bottom surface, and the second chip pad being on the second top surface of the second semiconductor substrate
a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad of the first semiconductor chip
a connection substrate on a top surface of the lower redistribution structure and including and a conductive connection structure and a substrate base having an accommodation space exposing the top surface of the lower redistribution structure and accommodating the first semiconductor chip and the second semiconductor chip therein, wherein the conductive connection structure passes through the substrate base
a molding layer covering the first semiconductor chip and the second semiconductor chip
an upper redistribution structure including an upper redistribution insulating layer and an upper redistribution pattern, the upper redistribution pattern including an upper redistribution line pattern and a first upper redistribution via pattern, the upper redistribution line pattern extending along a top surface of the molding layer, and the first upper redistribution via pattern extending from the top surface of the molding layer toward the second semiconductor chip and being connected to the second chip pad of the second semiconductor chip
a conductive connection structure electrically connecting the lower redistribution pattern of the lower redistribution structure to the upper redistribution pattern of the upper redistribution structure
wherein the first upper redistribution via pattern has a tapered shape having a horizontal width decreasing toward the second chip pad of the second semiconductor chip, and wherein the first lower redistribution via pattern has a tapered shape having a horizontal width decreasing toward the first chip pad of the first semiconductor chip
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/N.R.P/ 8/8/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights