Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee at al. (US20200135594A1, hereinafter Lee).
Regarding claim 10, Lee discloses a semiconductor package, comprising:
a first semiconductor chip (See below annotated fig. 3 first chip 200); and
a second semiconductor chip on the first semiconductor chip (See below annotated fig. 3 second chip 300 on first chip 200),
wherein the first semiconductor chip includes an upper bonding pad and an upper test pad (See below annotated fig. 3 first chip 200 has upper bonding pad P1b and upper test pad P1a),
wherein the second semiconductor chip includes:
a lower bonding pad in contact with the upper bonding pad (See below annotated fig. 3 second chip 300 has lower bonding pad P2b in contact with upper bonding pad P1b); and
a lower test pad in contact with the upper test pad (See below annotated fig. 3 second chip 300 has lower test pad P2a in contact with upper test pad P1a),
wherein the upper test pad includes:
a plurality of first long sidewalls that extend parallel to each other (See below annotated fig. 3 plurality of first long sidewalls INS1 that extend parallel to one another); and
a plurality of first short sidewalls that extend in parallel to each other (See below annotated fig. 3 plurality of first short sidewalls INS1 that extend parallel to one another),
wherein the lower test pad includes:
a plurality of second long sidewalls that extend in parallel to each other (See below annotated fig. 3 plurality of second long sidewalls INS2 that extend parallel to one another); and
a plurality of second short sidewalls that extend in parallel to each other (See below annotated fig. 3 plurality of second short sidewalls INS2 that extend parallel to one another),
wherein the plurality of first short sidewalls are shorter than the plurality of first long sidewalls (See below annotated fig. 3 plurality of first short sidewalls INS1 are shorter than the plurality of first long sidewalls INS1), and
wherein the plurality of second short sidewalls are shorter than the plurality of second long sidewalls (See below annotated fig. 3 plurality of second short sidewalls INS2 are shorter than the plurality of second long sidewalls INS1).
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Regarding claim 11, Lee discloses the semiconductor package of claim 10,
wherein the plurality of first long sidewalls overlap the second long sidewalls (See above annotated fig. 3 the plurality of first long sidewalls INS1 overlap the plurality of second long sidewalls INS2).
Regarding claim 12, Lee discloses the semiconductor package of claim 10,
wherein the plurality of first short sidewalls are offset from the lower test pad (See above annotated fig. 3 plurality of first short sidewalls INS1 are offset from lower test pad P2a), and
the plurality of second short sidewalls are offset from the upper test pad (See above annotated fig. 3 plurality of second short sidewalls INS1 are offset from upper test pad P1a).
Regarding claim 13, Lee discloses the semiconductor package of claim 10,
wherein the upper test pad includes a first upper test pad and a second upper test pad (See above annotated fig. 3 there is an additional test pad TP on the right side of first chip 200),
wherein the first upper test pad extends in a first direction, and wherein the second upper test pad extends in a second direction that intersects the first direction (See above annotated fig. 3 as test pads TP are squares, they both extend in two directions and so a left test pad extends in an x-direction and the right test pad TP extends in an intersecting y-direction).
Regarding claim 14, Lee discloses the semiconductor package of claim 13,
wherein the upper bonding pad is between the first upper test pad and the second upper test pad (See above annotated fig. 3 upper bonding pad P1b is between the left and right test pads TP).
Regarding claim 15, Lee discloses the semiconductor package of claim 13,
wherein the lower test pad includes:
a first lower test pad in contact with the first upper test pad (See above annotated fig. 3 left lower test pad P2a in contact with left upper test pad P1a); and
a second lower test pad in contact with the second upper test pad (See above annotated fig. 3 right lower test pad P2a in contact with right upper test pad P1a),
wherein the first lower test pad extends in the second direction, and wherein the second lower test pad extends in the first direction (As both lower test pads P2a are square shaped the left lower test pad extends in an x-direction and the right pad extends in a y-direction).
Regarding claim 16, Lee discloses the semiconductor package of claim 10,
wherein the upper test pad further includes a connection surface that connects the first long sidewall to the first short sidewall (Fig. 4 illustrates a plan view of the test pad regions and illustrate that the first long sidewalls and first short sidewalls between these connections are connected by portions of INS1 not illustrated in the plane shown in fig. 3).
Regarding claim 17, Lee discloses the semiconductor package of claim 16,
wherein the connection surface is curved (As first long sidewalls and first short sidewalls are connected by a connecting portion that extends perpendicular to the plane illustrated in fig. 3 as well as in an x-direction then that connection surface takes a curved path and is curved).
Allowable Subject Matter
Claims 1-9 and 19-20 allowed.
Claim 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1 and its dependent claims. The closest prior art (US20200135594A1, US20080006938A1, US20210104482A1) teaches a semiconductor package, comprising:
a first semiconductor chip (See above annotated Lee fig. 3 first chip 200); and
a second semiconductor chip on the first semiconductor chip (See above annotated Lee fig. 3 second chip 300 on first chip 200),
wherein the first semiconductor chip includes:
an upper bonding pad (See above annotated fig. 3 first chip 200 has upper bonding pad P1b);
an upper test pad (See above annotated fig. 3 first chip 200 has upper test pad P1a); and
an upper dielectric layer that surrounds the upper bonding pad and the upper test pad (See above annotated fig. 3 first dielectric layer INS1 surrounding upper bonding pad P1b and upper test pad P1a),
wherein the second semiconductor chip includes:
a lower bonding pad in contact with the upper bonding pad (See above annotated fig. 3 second chip 300 has lower bonding pad P2b in contact with upper bonding pad P1b);
a lower test pad in contact with the upper test pad (See above annotated fig. 3 second chip 300 has lower test pad P2a in contact with upper test pad P1a); and
a lower dielectric layer that surrounds the lower bonding pad and the lower test pad (See above annotated fig. 3 second dielectric layer INS2 surrounding upper bonding pad P2b and upper test pad P2a),
wherein the upper test pad includes:
a first overlapping portion that overlaps the lower test pad (See above annotated fig. 3 upper test pad P1a has overlapping portion that overlaps lower test pad P2a); and
a plurality of second overlapping portions that overlap the lower dielectric layer (See above annotated fig. 3 upper test pad further comprises connection portions IPa which overlap second dielectric INS2 on the left and right edges),
wherein the first overlapping portion is between the plurality of second overlapping portions (See above annotated fig. 3 portions of upper test pad P1a that overlaps lower test pad P2a is between the left and right connection portions IPa which are disposed on the edges),
wherein the lower test pad includes:
a third overlapping portion that overlaps the first overlapping portion of the upper test pad (See above annotated fig. 3 lower test pad P2a has first overlapping portion which overlaps upper test pad P1a); and
However, the closest prior art does not teach in combination with the other claimed elements
wherein the lower test pad includes a plurality of fourth overlapping portions that overlap the upper dielectric layer, wherein the third overlapping portion is between the plurality of fourth overlapping portions.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Regarding claim 18, the closest prior art (US20200135594A1, US20080006938A1, US20210104482A1) teaches the semiconductor package of claim 10,
wherein the first semiconductor chip includes:
a plurality of first sidewalls that are in parallel to each other (See above annotated fig. 3 first semiconductor body 205 has left sidewalls of each of the through vias that are parallel to one another); and
a plurality of second sidewalls that are in parallel to each other (See above annotated fig. 3 first semiconductor body 205 has right sidewalls of each of the through vias that are parallel to one another).
However, the closest prior art does not teach in combination with the other claimed elements
wherein the plurality of first long sidewalls are parallel to the plurality of first sidewalls of the first semiconductor chip, and wherein the plurality of first short sidewalls are parallel to the plurality of second sidewalls of the first semiconductor chip.
Regarding claim 19 and its dependent claim. The closest prior art (US20200135594A1, US20080006938A1, US20210104482A1) teaches a semiconductor package, comprising:
a first semiconductor chip (See above annotated Lee fig. 3 first chip 200); and
a second semiconductor chip on the first semiconductor chip (See above annotated Lee fig. 3 second chip 300 on first chip 200),
wherein the first semiconductor chip includes:
a first lower dielectric layer (See above annotated Lee fig. 3 first chip 200 has lower dielectric layer INS2);
a first wiring structure on the first lower dielectric layer (See above annotated Lee fig. 3 first chip 200 has wiring structure disposed above lower dielectric layer INS2);
a first substrate on the first wiring structure (See above annotated Lee fig. 3 first chip 200 has first semiconductor body 205);
a through via that penetrates the first substrate (See above annotated Lee fig. 3 first chip 200 has through via that penetrates through first semiconductor body 205);
an upper dielectric layer on the first substrate (See above annotated Lee fig. 3 first chip 200 has upper dielectric layer INS1); and
an upper bonding pad and an upper test pad that are surrounded by the upper dielectric layer (See above annotated fig. 3 first chip 200 has upper test pad P1a and upper bonding pad P1b),
wherein the second semiconductor chip includes:
a lower bonding pad in contact with the upper bonding pad (See above annotated Lee fig. 3 second chip 300 has lower bonding pad P2b in contact with upper bonding pad P1b);
a lower test pad in contact with the upper test pad (See above annotated Lee fig. 3 second chip 300 has lower test pad P2a in contact with upper test pad P1a);
a second lower dielectric layer that surrounds the lower bonding pad and the lower test pad (See above annotated Lee fig. 3 second chip 300 has lower dielectric layer INS2);
a second wiring structure on the second lower dielectric layer (See above annotated Lee fig. 3 second chip 300 has wiring structure disposed on lower dielectric layer INS2); and
a second substrate on the second wiring structure (See above annotated Lee fig. 3 second chip 300 has second semiconductor body 305),
wherein the upper test pad includes:
a first overlapping portion in contact with the lower test pad (See above annotated fig. 3 upper test pad P1a has overlapping portion in contact with lower test pad P2a); and
wherein a sidewall of the first overlapping portion is coplanar with sidewalls of the plurality of second overlapping portions (See above annotated fig. 3 sidewalls of upper test pad P1a are coplanar with portion in contact with lower test pad P2a).
However, the closest prior art does not teach in combination with the other claimed elements
wherein the upper test pad includes a plurality of second overlapping portions in contact with the second lower dielectric layer, and
wherein a sidewall of the first overlapping portion is coplanar with sidewalls of the plurality of second overlapping portions.
Additionally, the closest prior art does not teach the above in combination with the further limitations of the dependent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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