DETAILED ACTION
This Office Action is in response to Applicant’s application 18/765,981 filed on July 8, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on July 8, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on July 8, 2024 and March 21, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2022/0416055 (Maeng) and U.S. 2022/0093603 (Cho).
Regarding claim 19 and referring to annotated Figures 5 and 9B, Maeng discloses a semiconductor device, comprising:
a substrate, 501 [0119];
a plurality of conductive contacts, 421 [0124], on the substrate, as shown; and
a plurality of capacitors, 600 [0126], on the conductive contacts, as shown,
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626
526
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Greyscale
wherein each of the capacitors includes:
a bottom electrode, 101 [0076];
a dielectric layer, 332 [0081, 84] /320 [0076-77] on the bottom electrode, as shown; and
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516
607
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Greyscale
a top electrode, 102 [0080], on the dielectric layer, as shown, wherein the dielectric layer includes a first sub-dielectric layer, 332 [0081, 84], and a second sub-dielectric layer, 320 [0077], that are sequentially stacked, as shown, wherein the second sub-dielectric layer includes:
a first antiferroelectric layer, 321 [0081], on the first sub-dielectric layer, as shown;
a second antiferroelectric layer, 322 [0081], on the first antiferroelectric layer, as shown; and
a first ferroelectric layer, 323 [0079], between the first antiferroelectric layer and the second antiferroelectric layer, as shown, wherein the first sub-dielectric layer has a first thickness, as shown, wherein the first ferroelectric layer has a second thickness, as shown, wherein each of the first and second antiferroelectric layers has a third thickness, as shown.
At [0081], Meang teaches the thickness of ferroelectric layer 323 is less than the thickness of antiferroelectric layers 321 or 322.
Maeng does not explicitly teach each of the first, second, and third thicknesses is in a range of about 5 Å to about 15 Å.
Cho is directed to ferroelectric capacitors. At [0038-39], Cho teaches a suitable thickness for a ferroelectric layer is 5 to 18 Å
Taken as a whole the prior art is directed to implementation of 1T1C memory cells. Cho teaches that a thickness of a ferroelectric layer in a memory capacitor may be 5-18 Å and Meang teaches that the antiferroelectric layer thicknesses are less than the ferroelectric layer, or less than 5-18 Å. Examiner also notes that the thickness of dielectric layers is a parameter to modulate the ferroelectric or antiferroelectric properties of the film, see U.S. 2021/0359082 (Kang) at [0043].
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 19 wherein each of the first, second, and third thicknesses is in a range of about 5 Å to about 15 Å because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990). See MPEP 2144.05.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 20 the prior art fails to disclose the device of claim 19, wherein a first element is doped into the first and second antiferroelectric layers, the first element including at least one element selected from Al, Mg, Be, Y, La, Ca, C, Si, Ge, Sn, Pb, Gd, and Ti, and wherein the first ferroelectric layer comprises a material other than the first element.
Claims 1-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art fails to disclose a semiconductor device comprising a capacitor, wherein the capacitor includes: a bottom electrode; a first sub-dielectric layer on the bottom electrode; a second sub-dielectric layer on the first sub-dielectric layer; and a top electrode on the second sub-dielectric layer, wherein the second sub-dielectric layer includes: a first antiferroelectric layer on the first sub-dielectric layer; a second antiferroelectric layer above the first antiferroelectric layer; and a first ferroelectric layer between the first antiferroelectric layer and the second antiferroelectric layer, wherein each of the first and second antiferroelectric layers includes zirconium oxide that is doped with a first element, and wherein the first sub-dielectric layer includes zirconium oxide that is not doped with the first element.
Regarding claim 10 the prior art fails to disclose a semiconductor device, comprising: a substrate; a plurality of word lines in the substrate; a first impurity region in the substrate on one side of each of the word lines; a second impurity region in the substrate between the word lines; a bit line connected to the second impurity region and on the substrate, the bit line perpendicular to the word lines; a conductive contact connected to the first impurity region and on the substrate; a bottom electrode on the conductive contact; a dielectric layer on the bottom electrode; a top electrode on the dielectric layer; and a support pattern in contact with an upper lateral surface of the bottom electrode, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer that are sequentially stacked, wherein the second sub-dielectric layer includes: a plurality of antiferroelectric layers on the first sub-dielectric layer; and at least one or more ferroelectric layers correspondingly between the antiferroelectric layers, wherein each of the antiferroelectric layers includes zirconium oxide that is doped with a first element, wherein the first sub-dielectric layer includes zirconium oxide that is not doped with the first element, and wherein a sum of thicknesses of the ferroelectric layers is about 0.2 times to about 0.4 times a thickness of the dielectric layer.
Claims 2-9 and 11-18 depend directly or indirectly on claims 1 or 10 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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