DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8-10, 12, 15, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160360225 A1 Diggins; Jonathan et al. (hereafter Diggins), and further in view of US 20180205909 A1 Staranowicz; Aaron et al. (hereafter Staranowicz).
Regarding claim 1, Diggins discloses A processor (Fig.8), comprising: one or more circuits ([127]) to: identify a pixel cluster including a plurality of pixels of a first video frame based, at least in part on (Fig.2, [24], area of similar pixel is the clustered pixel): a pixel location in the first video frame having one or more forward motion vectors that
Diggins fails to disclose a pixel intensity at the pixel location; and generate a new pixel for an intermediate video frame between the first video frame and the second video frame based, at least in part, on the identified pixel cluster.
However, Staranowicz teaches a pixel intensity at the pixel location ([40], [45]); and generate a new pixel for an intermediate video frame between the first video frame and the second video frame based, at least in part, on the identified pixel cluster ([03], [42], intermediate image is a result of interpolation between first and second image frames).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the processor disclosed by Diggins to include the teaching in the same field of endeavor of Staranowicz, in order to obtain a high degree of accuracy for the produced intermediate frame between two frames, as identified by Staranowicz.
Regarding claims 8, 17, Diggins discloses The processor of claim 1, wherein the one or more circuits are further to traverse the plurality of pixels using at least one of a first buffer or a second buffer and an array of coordinates, wherein the first buffer includes a first value wherein bits corresponding to the first value indicate current level coordinates using the array of coordinates, and wherein the second buffer includes a second value wherein bits corresponding to the second value indicate next level coordinates using the array of coordinates (Fig.8, [87]).
Regarding claims 9, 12, Diggins discloses The processor of claim 1, wherein the one or more circuits are further configured to interpolate two or more video frames using the plurality of pixels ([07]).
Regarding claims 10, 19, see the rejection for claim 1.
Regarding claim 15, Diggins discloses The system of claim 10, wherein the one or more circuits are further to determine that the plurality of pixels meets a criterion ([10]).
Regarding claim 18, Staranowicz teaches The system of claim 10, wherein the one or more circuits are further to determine a time difference between two or more video frames to interpolate the two or more video frames ([36]).
Claim(s) 2-4, 11, 13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Diggins, in view of Staranowicz, and further in view of US 20230281843 A1 Wu; Tiecheng et al. (hereafter Wu).
Regarding claims 2, 11, 20, Wu teaches The processor of claim 1, wherein the one or more circuits are further to determine a cost to infill valid motion vectors for the pixel location based, at least in part, on the plurality of pixels ([14], [56]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention having all the references Diggins, Staranowicz and Wu before him/her, to modify the processor disclosed by Diggins to include the teaching in the same field of endeavor of Staranowicz and Wu, in order to obtain a high degree of accuracy for the produced intermediate frame between two frames, as identified by Staranowicz, and reduce computation cost but maintain a high level of accuracy when generating depth images, as identified by Wu.
Regarding claim 3, Wu teaches The processor of claim 1, wherein the one or more circuits are further to determine coordinates associated with the pixel location ([78]).
Regarding claims 4, 13, Wu teaches The processor of claim 1, wherein the one or more circuits are further to generate a gradient map for the first video frame ([66]-[68]).
Claim(s) 5, 7, 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Diggins, in view of Staranowicz, and further in view of US 20180144476 A1 Smith.
Regarding claims 5, 14, Smith teaches The processor of claim 1, wherein the one or more circuits are further configured to identify the plurality of pixels using a gradient map and intensity information from the first video frame ([140], [176]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention having all the references Diggins, Staranowicz and Smith before him/her, to modify the processor disclosed by Diggins to include the teaching in the same field of endeavor of Staranowicz and Smith, in order to obtain a high degree of accuracy for the produced intermediate frame between two frames, as identified by Staranowicz, and provide efficient and robust video sequence processing, as identified by Smith.
Regarding claims 7, 16, Smith teaches The processor of claim 1, wherein the one or more circuits are further to identify the plurality of pixels based at least in part on downsampled versions of the first video frame and the second video frame ([10]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Diggins, in view of Staranowicz, and further in view of US 20180139443 A1 PARK; Min-woo et al. (hereafter Park).
Regarding claim 6, Park teaches The processor of claim 1, wherein the one or more circuits are further to use a first criterion to group edge coordinates, determined from an edge detection operation, with neighbor edge coordinates and to use a second criterion to group non-edge coordinates with neighboring non-edge coordinates ([102]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention having all the references Diggins, Staranowicz and Park before him/her, to modify the processor disclosed by Diggins to include the teaching in the same field of endeavor of Staranowicz and Park, in order to obtain a high degree of accuracy for the produced intermediate frame between two frames, as identified by Staranowicz, and increase encoding efficiency and also increase transmission efficiency, as identified by Park.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY Y. LI whose telephone number is (571)270-3671. The examiner can normally be reached Monday Friday (8:30 AM- 4:30 PM) EST.
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/TRACY Y. LI/Primary Examiner, Art Unit 2487