DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 24-26 and 28-38 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park (U.S. Patent No. 12,334,471).
Regarding to claim 24, Park teaches a method of manufacturing a semiconductor device, the method comprising:
forming a first stack on a first substrate (Fig. 14B);
forming first channel structures extending into the first substrate through the first stack (Fig. 14C; element 240; column 24, lines 47-50);
forming a first contact plug extending through the first stack (Fig. 14F, element 260; column 25, lines 21-23);
removing the first substrate (column 27, lines 65-66);
forming a first dielectric bonding layer on the first stack (Fig. 14F, column 25, lines 62-64);
forming first openings exposing the first channel structures by partially removing the first dielectric bonding layer (column 25, lines 65-67);
forming a second opening exposing the first contact plug by partially removing the first dielectric bonding layer (column 26, lines 4-6);
forming first source bonding patterns in the first openings (Fig. 14F, column 26, lines 1-3); and
forming a first contact bonding pattern in the second opening (Fig. 14F, column 26, lines 12-15).
Regarding to claim 25, Park teaches when forming the first openings, the second opening is formed (Fig. 14F).
Regarding to claim 26, Park teaches when forming the first source bonding patterns, the first contact bonding pattern is formed (Fig. 14F).
Regarding to claim 28, Park teaches
forming a first cell wafer including the first source bonding patterns, the first contact bonding pattern, the first dielectric bonding layer, the first contact plug, and the first channel structures (Fig. 14H, element Cell2);
forming a second cell wafer including a second stack, a second gate structure, second channel structures extending through the second gate structure, a second contact plug extending through the second stack, a second dielectric bonding layer formed on the second stack, second source bonding patterns formed on the second gate structure, and a second contact bonding pattern formed on the second stack (Fig. 14H, element Cell1); and
bonding the first cell wafer and the second cell wafer so that the first source bonding patterns and the second source bonding patterns are connected, the first contact bonding pattern and the second contact bonding pattern are connected, and the first dielectric bonding layer and the second dielectric bonding layer are connected (Fig. 15H, Fig. 13).
Regarding to claim 29, Park teaches the second contact plug is electrically connected to the second contact bonding pattern, the first contact bonding pattern, and the first contact plug (Fig. 13).
Regarding to claim 30, Park teaches the first stack includes first material layers and second material layers alternately stacked, the first stack includes a first step structure exposing an upper surface of each of the second material layers, and the method further comprises forming first contact vias extending through the first step structure and respectively connected to the second material layers, before removing the first substrate (Fig. 13).
Regarding to claim 31, Park teaches the second stack includes third material layers and fourth material layers alternately stacked, and the second stack includes a second step structure exposing an upper surface of each of the fourth material layers, and wherein the second cell wafer further includes second contact vias extending through the second step structure and respectively connected to the fourth material layers (Fig. 13, stack 230).
Regarding to claim 32, Park teaches the first cell wafer further includes third contact bonding patterns formed at a level corresponding to the first source bonding patterns, wherein the second cell wafer further includes fourth contact bonding patterns formed at a level corresponding to the second source bonding patterns, and wherein the second contact vias are electrically connected to the fourth contact bonding patterns, the fourth contact bonding patterns, and the first contact vias (Fig. 13).
Regarding to claim 33, Park teaches the first stack includes first material layers and second material layers alternately stacked, the first stack includes a first step structure exposing an upper surface of each of the second material layers, and the method further comprises forming first contact vias directly connected to an upper surface of each of the second material layers and having different heights, before removing the first substrate (Figs. 14E-F).
Regarding to claim 34, Park teaches the second stack includes third material layers and fourth material layers alternately stacked, the second stack includes a second step structure exposing an upper surface of each of the fourth material layers, and wherein the second cell wafer further includes second contact vias directly connected to the upper surface of each of the fourth material layers and having different heights (Fig. 13).
Regarding to claim 35, Park teaches the first cell wafer further includes a third stack formed at a level corresponding to the first stack, a fifth contact bonding pattern formed at a level corresponding to the first source bonding patterns, and a third contact plug extending into the fifth contact bonding pattern through the third stack, wherein the second cell wafer further includes a fourth stack formed at a level corresponding to the second stack, a sixth contact bonding pattern formed at a level corresponding to the second source bonding patterns, and a fourth contact plug extending into the sixth contact bonding pattern through the fourth stack, and wherein the second contact vias are electrically connected to the fourth contact plug, the sixth contact bonding pattern, and the fifth contact bonding pattern (Fig. 13).
Regarding to claim 36, Park teaches the first stack includes first material layers and second material layers alternately stacked, and the method further comprises forming first contact vias extending through the first stack and connected to the second material layers (Fig. 13).
Regarding to claim 37, Park teaches the second stack includes third material layers and fourth material layers alternately stacked, and wherein the second cell wafer further includes second contact vias extending through the second stack and connected to the fourth material layers (Fig. 13).
Regarding to claim 38, Park teaches the first cell wafer further includes a third stack formed at a level corresponding to the first stack, a fifth contact bonding pattern formed at a level corresponding to the first source bonding patterns, and a third contact plug extending into the fifth contact bonding pattern through the third stack, wherein the second cell wafer further includes a fourth stack formed at a level corresponding to the second stack, a sixth contact bonding pattern formed at a level corresponding to the second source bonding patterns, and a fourth contact plug extending into the sixth contact bonding pattern through the fourth stack, and wherein the second contact vias are electrically connected to the fourth contact plug, the sixth contact bonding pattern, and the fifth contact bonding pattern (Fig. 13).
Allowable Subject Matter
Claims 1-23 are allowed.
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 27, the prior art fails to anticipate or render obvious the claimed limitations including “annealing the conductive bonding layer and forming the first source bonding patterns in the first openings by planarizing the conductive bonding layer using the first dielectric bonding layer as a planarization barrier” in combination with the limitations recited in claim 24 and the rest of limitation recited in claim 27.
Regarding to claim 1, the prior art fails to anticipate or render obvious the claimed limitations including “a first gate structure positioned over the peripheral circuit and including first insulating layers and first conductive layers alternately stacked” in combination with “a first stack positioned at a level corresponding to the first gate structure and including the first insulating layers and first sacrificial layers alternately stacked”.
Comparing to the prior-art of the record, the most relevant prior art is Furihata et al. (U.S. Patent No. 10,038,006). Furihata discloses the claimed invention except for the limitations listed above. In particular, in Fig. 76, Furihata discloses a first gate structure positioned over the peripheral circuit and including first insulating layers 132 and first conductive layers 146 alternately stacked; a first stack positioned at a level corresponding to the first gate structure and including first insulating layers 132 and first conductive layers 146 alternately stacked. Otherwise, in Fig. 10A, Furihata discloses a first gate structure positioned over the peripheral circuit and including first insulating layers 132 and first sacrificial layers 142 alternately stacked; a first stack positioned at a level corresponding to the first gate structure and including the first insulating layers 132 and first sacrificial layers 142 alternately stacked. Furihata does not disclose one stack including sacrificial layers while another stack including conductive layer. The rest of limitations of claim 1 is disclosed by Fig. 17 of Furihata.
Claims 2-23 are allowable for the same reasons with claim 1.
Pertinent Art
For the benefits of the Applicant, US-20240222267-A1, US-20250385179-A1, US-11049847-B2, US-11943916-B2, and US-10985178-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The cited references fail to disclose “a first gate structure positioned over the peripheral circuit and including first insulating layers and first conductive layers alternately stacked” in combination with “a first stack positioned at a level corresponding to the first gate structure and including the first insulating layers and first sacrificial layers alternately stacked”.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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