Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 07/09/24. Claims 1-15 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. §103 as being unpatentable over DU (CN 212209497U) and further in view of Chen (US 2023/0223494 A1).
Regarding claim 1, Du discloses a light-emitting substrate (see para [0024]-[0056] figs 1-3), comprising: a driving backplane (11 a backplane); a plurality of light-emitting chips (10a LED Chips); and a grating structure (see grating structure, paras [0030]-[0037]), on a side of the plurality of light-emitting chips facing away from the driving backplane (see figs 1-3), wherein the grating structure has a plurality of regions (see 20a-c), and the plurality of regions is configured to transmit light of different wavelength bands (see 20a-c corresponding to colors, fig 2).
However, Du does not explicitly disclose that the device is arranged on the driving backplane in an array, wherein each light-emitting chip comprises a buffer layer, an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer sequentially arranged on the driving backplane in a stacked manner.
However, Chen discloses the device is arranged on the driving backplane in an array, wherein each light-emitting chip comprises a buffer layer 104, an N-type semiconductor layer, a multi-quantum well layer (602), and a P-type semiconductor layer 604 sequentially arranged on the driving backplane in a stacked manner (see fig 11 and fig 1 disclosing sequential arrangement).
Du and Chen are in the same or similar fields of endeavor. It would have been obvious to one ordinary skill in the art at a time prior to the effective filing date of the present application to combine Du with Chen. Du and Chen may be combined by forming the device of Du in accordance with Chen by forming the LED device in the order disclosed in Chen. One having ordinary skill in the art would be motivated to combine Du with Chen in order to produce a conventional LED device.
Regarding claim 2, Du and Chen disclose the light-emitting substrate according to claim 1, Du further discloses wherein each region in the grating structure satisfies at least one of: each region corresponding to a different grating period; each region corresponding to a same grating period(see 20a-c corresponding to colors, fig 2), each region corresponding to a same grating height(see 20a-c disclosing same height, fig 2), and each region corresponding to a different grating width (see width is narrow in grating area); or each region corresponding to a same grating period, each region corresponding to a same grating width, and each region corresponding to a different grating height (see 20a-c disclosing grating dimensions, fig 2).
Regarding claim 3, Du and Chen disclose the light-emitting substrate according to claim 2, wherein the plurality of regions is provided in one-to-one correspondence with the light-emitting chip, or the plurality of regions are provided in correspondence with one light-emitting chip(see 20a-c corresponding to chips, fig 2).
Regarding claim 4, Du and Chen discloses the light-emitting substrate according to claim 3, wherein the plurality of regions comprise a first region, a second region, and a third region; the first region is configured to transmit light of a first wavelength band, the second region is configured to transmit light of a second wavelength band, the third region is configured to transmit light of a third wavelength band; and a wavelength of the first wavelength band is greater than a wavelength of the second wavelength band, and the wavelength of the second wavelength band is greater than a wavelength of the third wavelength band(see 20a-c corresponding to colors, fig 2).
Regarding claim 5, Du and Chen discloses the light-emitting substrate according to claim 4, wherein the grating structure comprises a first metal layer, a dielectric layer, and a metal line grid layer sequentially arranged in a stacked manner, and the metal line grid layer comprises a plurality of metal lines arranged at intervals(see 21-22 in 20a-c corresponding to colors, fig 2).
Regarding claim 6, Du and Chen disclose the light-emitting substrate according to claim 5, wherein a grating period of the metal line grid layer corresponding to the first region, a grating period of the metal line grid layer corresponding to the second region, and a grating period of the metal line grid layer corresponding to the third region sequentially decrease(see 20a-c corresponding to colors, fig 2).
Regarding claim 7, Du and Chen disclose the light-emitting substrate according to claim 6, wherein a gap between adjacent metal lines has a same width, and a width of the metal line corresponding to the first region, a width of a metal line corresponding to the second region, and a width of a metal line corresponding to the third region sequentially decrease; or all the metal lines have a same width, a width of a gap between adjacent metal lines corresponding to the first region, a width of a gap between adjacent metal lines corresponding to the second region, and a width of a gap between adjacent metal lines corresponding to the third region sequentially decrease (see 20a-c corresponding to colors having different gaps in between devices, fig 2).
Regarding claim 8, Du and Chen disclose the light-emitting substrate according to claim 7, wherein the first metal layer is proximate to the light-emitting chip; or the metal line grid layer is proximate to the light-emitting chip, and the grating structure further comprises a second metal layer between the metal line grid layer and the light-emitting chip(see 20a-c corresponding to colors being over/proximate to the emitting layers, fig 2).
Regarding claim 9, Du and Chen disclose the light-emitting substrate according to claim 5, wherein the first metal layer is proximate to the light-emitting chip, grating periods of the metal line grid layer respectively corresponding to the first region, the second region, and the third region are the same, and a width of a metal line corresponding to the first region(see 20a-c corresponding to colors being over/proximate to the emitting layers, fig 2), a width of a metal line corresponding to the second region and a width of a metal line corresponding to the third region sequentially decrease(see 20a-c having different widths between devices, fig 2).
Regarding claim 10, Du and Chen disclose the light-emitting substrate according to claim 5, wherein the first metal layer is proximate to the light-emitting chip, grating periods of the metal line grid layer respectively corresponding to the first region, the second region, and the third region are the same, widths of the plurality of metal lines are the same(see 20a-c corresponding to colors being over/proximate to the emitting layers, fig 2), and a height of a metal line corresponding to the first region, a height of a metal line corresponding to the second region and a height of a metal line corresponding to the third region sequentially decrease (see fig 2, disclosing recess height of each metal line, in sequence).
Regarding claim 11, Du and Chen disclose the light-emitting substrate according to claim 4, wherein the grating structure comprises a first metal layer, a dielectric line grid layer, and a third metal layer sequentially arranged in a stacked manner, the dielectric line grid layer comprises a plurality of dielectric lines arranged at intervals(see 20a-c corresponding to colors being over intervals to the emitting layers, fig 2), a grating period of the dielectric line grid layer corresponding to the first region, a grating period of the dielectric line grid layer corresponding to the second region and a grating period of the dielectric line grid layer corresponding to the third region sequentially decrease(see 20a-c corresponding to colors being over/proximate to the emitting layers, spacing varying, fig 2).
Regarding claim 12, Du and Chen disclose the light-emitting substrate according to claim 11, wherein a material of the dielectric line grid layer comprises SiO or SiN (see description of element 40, disclosing silicon oxide).
Regarding claim 13, Du and Chen disclose the light-emitting substrate according to claim 11, wherein a material of the dielectric line grid layer is a rigid substrate material or a flexible substrate material, the grating structure further comprises a first substrate between the dielectric line grid layer and the third metal layer, and the first substrate and the dielectric line grid layer are a one-piece structure(see 20a-c corresponding to colors being over/proximate to the emitting layers, fig 2).
Regarding claim 14, Du and Chen disclose a light-emitting substrate according to claim 1, wherein the driving backplane is a silicon-based driving backplane, and the light-emitting chip is a Micro LED or Mini LED (see description disclosing panel being Micro-Oled).
Regarding claim 15, Du and Chen disclose a display apparatus, comprising the light-emitting substrate according to claim 1 see fig 3 of Du.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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