DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figs. 6-8E; claims 1-8, 11-16 and 19) in the reply filed on 8.27.2026 is acknowledged.
Claims 9-10 and 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8.27.2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7.9.2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yong et al. (US 20200357744 A1).
Regarding claim 1, Yong discloses a semiconductor package (Fig. 2A) comprising:
a package board (242);
a first semiconductor chip (210A) disposed on the package board, and having a first recess portion (211) adjacent (near) to a first front surface (bottommost at 218) of the first semiconductor chip facing the package board;
a second semiconductor chip (210B) disposed side by side with the first semiconductor chip on the package board, and having a second recess portion (211) adjacent (near) to a second front surface (bottommost at 218) of the second semiconductor chip facing the package board; and
an interconnect bridge (220) disposed on (indirectly) the first and second front surfaces, and at least partially disposed in each of the first and second recess portions (211, Fig. 2A).
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Regarding claim 7, Yong discloses the semiconductor package of claim 1, further comprising a plurality of second contact members (222/223) respectively connecting the interconnect bridge (220) to the first and second semiconductor chips (210A/210B, Fig. 2A).
Regarding claim 11, Yong discloses a semiconductor package (Fig. 2A) comprising:
a package board (242);
first and second semiconductor chips (210A/210B) disposed on the package board;
a molding material (243) disposed on the package board, and at least partially filling a space between the first and second semiconductor chips (Fig. 2A);
a recess portion (211) extending through a portion of each of the first and second semiconductor chips and the molding material (Fig. 2A) in a vertical direction from a lower surface (near 214) of each of the first and second semiconductor chips and the molding material (Fig. 2A); and
an interconnect bridge (220) disposed in the recess portion.
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Regarding claim 12, Yong discloses the semiconductor package of claim 11, wherein the recess portion has a bottom surface (bottommost) including the lower surface (at 214) of each of the first and second semiconductor chips (210A/210B) and the molding material (243), and a wall surface (left/right) including an inner surface (at 216) of each of the first and second semiconductor chips (210A/210B), and
the bottom surface (bottommost) of the recess portion is substantially flat (Fig. 2A).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yong et al. (US 20200357744 A1).
Regarding claim 8, Yong discloses the semiconductor package of claim 7, wherein each of the plurality of second contact members (222/223) includes at least one of a
Yong fails to disclose metal as a material of a bump (222).
Metal is a well-known and commonly employed material employed in interconnect structures such as bumps 222 and it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include metal bumps as claimed in Yong so as to select a material capable of interconnecting different devices and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yong et al. (US 20200357744 A1) in view of Takahashi et al. (US 20200266229 A1).
Regarding claim 13, Yong fails to disclose the semiconductor package of claim 11, wherein the first semiconductor chip includes a first semiconductor board, a plurality of first transistor elements disposed on the first semiconductor board, a first insulating layer disposed on the first semiconductor board, and a plurality of first metal layers respectively disposed on or in the first insulating layer,
the second semiconductor chip includes a second semiconductor board, a plurality of second transistor elements disposed on the second semiconductor board, a second insulating layer disposed on the second semiconductor board, and a plurality of second metal layers respectively disposed on or in the second insulating layer, and
the plurality of first and second metal layers respectively include a plurality of first and second contact pads, each of which is at least partially exposed from a lower surface of each of the first and second insulating layers.
Takahashi discloses (Fig. 8) wherein the first semiconductor chip (712) includes a first semiconductor board (714), a plurality of first transistor elements (716a-c) disposed on the first semiconductor board, a first insulating layer (720) disposed on the first semiconductor board, and a plurality of first metal layers (at least 724 and 728) respectively disposed on or in the first insulating layer,
the second semiconductor chip (identical to 712) includes a second semiconductor board (identical to 714), a plurality of second transistor elements (identical to 716a-c) disposed on the second semiconductor board, a second insulating layer (identical to 720) disposed on the second semiconductor board, and a plurality of second metal layers (identical to at least 724 and 728) respectively disposed on or in the second insulating layer, and
the plurality of first and second metal layers (at least 724 and 728) respectively include a plurality of first and second contact pads (728), each of which is at least partially exposed from a lower surface of each of the first and second insulating layers (720. Note: the structure of 712 is applied to both the first and the second semiconductor chips of Yong).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the chip arrangement of Takahashi to both chips of Yong and arrive at the claimed invention so as to build chips with commonplace structures that allows for bonding of chips onto other devices.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yong et al. (US 20200357744 A1) in view of Takahashi et al. (US 20200266229 A1) as applied to claim 13 above, and further in view of Rubin et al. (US 10535608 B1).
Regarding claim 14, Yong/Takahashi fails to disclose the semiconductor package of claim 13, wherein the interconnect bridge includes an organic insulating layer, a plurality of metal wiring layers respectively disposed on or in the organic insulating layer, and at least one metal via layer disposed in the organic insulating layer and connecting the plurality of metal wiring layers to each other,
the metal wiring layers disposed on the uppermost and lowermost sides of the plurality of metal wiring layers respectively include a plurality of first and second connection pads, and
at least some portions of the plurality of first and second contact pads are respectively connected to the plurality of first connection pads.
Rubin discloses (Figs. 10 and 13) wherein the interconnect bridge (400) includes an (partly at least) organic insulating layer (312/322/332), a plurality of metal wiring layers (314 to 338) respectively disposed on or in the organic insulating layer, and at least one metal via layer (shown; not labeled) disposed in the organic insulating layer and connecting the plurality of metal wiring layers to each other (Fig. 10),
the metal wiring layers disposed on the uppermost and lowermost sides of the plurality of metal wiring layers respectively include a plurality of first (at 338) and second connection pads (at 314), and
at least some portions of the plurality of first and second contact pads (above 422/432 and part of 420/430) are respectively connected to the plurality of first connection pads (at 338.
Note: the examiner takes the position that Rubin implicitly discloses organic materials for the insulating layer and metal for the wiring layers/via layer/connection pads. In the event, Rubing does not implicitly do so, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include organic and metal materials as claimed because said materials are commonplace and their use would have yielded predictable results).
Finally, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the bridge disclosed/suggested by Rubin in Yong/Takahashi so as to achieve a bridge interconnection between chips.
Claims 1-2 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah et al. (US 20190229057 A1).
Regarding claim 1, Cheah discloses a semiconductor package (Figs. 1-2) comprising:
a package board (120);
a first semiconductor chip (110) disposed on the package board, and having a first recess portion (12) adjacent to a first front surface (117) of the first semiconductor chip facing the package board;
a second semiconductor chip (140) disposed side by side with the first semiconductor chip on the package board, and having a second recess portion (similar to 12) adjacent to a second front surface (similar to 117) of the second semiconductor chip facing the package board; and
an interconnect bridge (130; a bridge since it is between 110 and 140 and comprising interconnects 119) disposed on the first and second front surfaces, and at least partially disposed in each of the first and second recess portions (Figs. 1-2).
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Regarding claim 2, Cheah discloses the semiconductor package of claim 1, wherein the first and second recess portions (12) respectively extend through portions of the first and second semiconductor chips (110/140) from the first and second front surfaces (117) in a vertical (downward) direction, and are respectively exposed from inner surfaces (113/115) of the first and second semiconductor chips facing each other in a horizontal direction (Fig. 2).
Regarding claim 7, Cheah discloses the semiconductor package of claim 1, further comprising a plurality of second contact members (118) respectively connecting the interconnect bridge (130) to the first and second semiconductor chips (110/140, Figs. 1-2).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 20190229057 A1) in view of Waidhas et al. (US 20220199562 A1).
Regarding claim 3, Cheah fails to disclose the semiconductor package of claim 2, further comprising a molding material at least partially filling a space between the first and second semiconductor chips (110/1140),
wherein a third recess portion is disposed in a bottom of the molding material, and
the first and second recess portions (12) are connected to each other through the third recess portion.
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Waidhas discloses (Fig. 2B) a molding material (221) at least partially filling a space between the first and second semiconductor chips (225A/225B), and wherein a third recess portion (occupied by 227) is disposed in a bottom of the molding material (Fig. 2B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include a molding material in Fig. 1 of Cheah in view of Waidhas with the purpose of protecting semiconductor devices from external environments and prevent damage thereof.
Once 221 of Waidhas is applied to Fig. 1 of Cheah, “the first and second recess portions are connected to each other through the third recess portion” is met by the combination since 221 of Waidhas is applied to encapsulate 110, 130 and 140 of Cheah in the proposed modification.
Regarding claim 4, Cheah/Waidhas discloses (Fig. 2B) the semiconductor package of claim 3, wherein the molding material (221) covers an outer (sides) surface of each of the first and second semiconductor chips (225A and 225B), and
a lower surface (towards 227) of the molding material has a step by the third recess portion (occupied by 227. Fig. 2B; the placement of 227 creates a lower surface of 221 with a step).
Claims 5-6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 20190229057 A1) in view of Waidhas et al. (US 20220199562 A1) as applied to claim 3 above, and further in view of Yong et al. (US 20200357744 A1).
Regarding claim 5, Cheah/Waidhas discloses the semiconductor package of claim 3, further comprising a plurality of first contact members (122/124) connecting the first or second semiconductor chip (110/140) or the interconnect bridge (130) to the package board (120, Fig. 2).
Cheah/Waidhas fails to disclose an insulating material disposed to fill a space between at least one of the molding material, the first or second semiconductor chip, or the interconnect bridge and the package board, and covering the plurality of first contact members.
Yong discloses (Fig. 2A) an insulating material (243) disposed to fill a space between at least one of the molding material, the first or second semiconductor chip (210A/210B), or the interconnect bridge and the package board (242), and covering the plurality of first contact members (219).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to apply layer 243 of Yong in between 110/130/140 and 120 of Cheah and arrive at the claimed invention so as to passivate/protect contacts from exposure to an external environment.
Regarding claim 6, Cheah/Waidhas/Yong discloses the semiconductor package of claim 5, wherein each of the plurality of first contact members (219) includes a
Cheah/Waidhas/Yong fails to disclose a metal post.
Metal is a well-known and commonly employed material employed in interconnect structures such as posts 219 and it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include metal posts as claimed in Cheah/Waidhas/Yong so as to select a material capable of interconnecting different devices and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 20190229057 A1).
Regarding claim 8, Cheah discloses the semiconductor package of claim 7, wherein each of the plurality of second contact members (118) includes at least one of a
Cheah fails to disclose metal as a material of a bump (118).
Metal is a well-known and commonly employed material employed in interconnect structures such as bumps 118 and it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include metal bumps as claimed in Cheah so as to select a material capable of interconnecting different devices and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Allowable Subject Matter
Claims 15-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose or suggest (claim 15) wherein at least some other portions of the plurality of first and second contact pads and the plurality of second connection pads are respectively connected to the package board by using a plurality of first contact members, and the plurality of first contact members are embedded in an insulating material; claims 16 and 19 depend from claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210391273 A1 to Dubey et al. discloses a bridge (110) in between two electronic components (130, Fig. 2)
US 20220157727 A1 to Farooq et al. discloses a bridge (414) in stepped ends (408/412) of two ICs (406 and 410, Fig. 4)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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