Prosecution Insights
Last updated: October 02, 2026
Application No. 18/767,029

MOLD COMPOUND EMBEDDED DEVICE COOLING STRUCTURE

Non-Final OA §103
Filed
Jul 09, 2024
Examiner
NGUYEN, KHIEM D
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1928 granted / 2248 resolved
+17.8% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
60 currently pending
Career history
2283
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
28.8%
-11.2% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2248 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Mold compound embedded device cooling structure having a sealed two-phase cooling structure and method of fabricating the mold compound embedded device. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (U.S. Pub. 2020/0083143) in view of Shen (U.S. Pub. 2025/0062187). In re claim 1, Tsai discloses a packaged integrated circuit device comprising: a semiconductor die 32 (see paragraph [0073] and fig. 21); a sealed cooling structure 4m thermally coupled to the semiconductor die 32 (via a thermal adhesive material 34) (see paragraph [0078] and fig. 21); and a mold compound 68 encapsulating the semiconductor die 32 and the sealed cooling structure 4m (see paragraph [0080] and fig. 21). PNG media_image1.png 458 720 media_image1.png Greyscale Tsai is silent to wherein the sealed cooling structure is a sealed two-phase cooling structure. However, Shen discloses in a same field of endeavor, a packaged integrated circuit device including, inter-alia, a semiconductor die 805 (see paragraph [0036] and fig. 12); a sealed two-phase cooling structure (902a,902b,902c) thermally coupled to the semiconductor die 805 (see paragraph [0038] and fig. 12); and a mold compound 807 encapsulating the semiconductor die 805 (see paragraphs [0036], [0037] and fig. 12). PNG media_image2.png 490 629 media_image2.png Greyscale Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shen into the packaged integrated circuit device of Tsai in order to replace the sealed cooling structure in the packaged integrated circuit device of Tsai with the sealed two-phase cooling structure of Shen in order to directly dissipate heat from the semiconductor die to the upper part through a phase change manner and furthermore a vapor chamber that is adopted to quickly dissipate heat from the heat dissipating object to the outside of the vapor chamber can be obtain (see paragraph [0001] of Shen). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 2, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the package integrated circuit device further comprising an interface layer 34 between the sealed two-phase cooling structure 4m and the semiconductor die 32 (see paragraph [0074] and fig. 21 of Tsai). In re claim 3, as applied to claim 2 above, Tsai in combination with Shen discloses wherein the interface layer includes a layer of mold compound 68 (see paragraph [0080] and fig. 21 of Tsai, note that a portion of the mold compound 68 extended into the gap between the semiconductor die 32 and the sealed cooling structure 4m). In re claim 4, as applied to claim 2 above, Tsai in combination with Shen discloses wherein the interface layer 34 includes a thermal interface material (TIM) (see paragraph [0073] and fig. 21 of Tsai). In re claim 5, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the sealed two-phase cooling structure (902a,902b,902c) extends past an edge of the semiconductor die 805 (see paragraph [0038] and fig. 12 of Shen). In re claim 6, as applied to claim 1 above, Tsai in combination with Shen discloses wherein a face of the sealed two-phase cooling structure (902a,902b,902c) is adjacent to and aligned with a face of the semiconductor die 805, and wherein the face of the sealed two-phase cooling structure (902a,902b,902c) is at least as large as the face of the semiconductor die 805 (see paragraph [0038] and fig. 12 of Shen). Furthermore, it is respectfully submitted that, the configuration regarding about the shape of the face of the sealed two-phase cooling structure and the face of the semiconductor die was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)). Additionally, a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04. In re claim 7, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the sealed two-phase cooling structure includes a vapor chamber (see paragraph [0038] and fig. 12 of Shen). In re claim 8, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the sealed two-phase cooling structure includes one or more heat pipes (see paragraph [0067] and fig. 21 of Tsai). In re claim 9, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the packaged integrated circuit device further comprising a package substrate 806 (see paragraph [0036] and fig. 12 of Shen), the semiconductor die 805 attached to the package substrate 806, wherein the semiconductor die 805 is between the package substrate 806 and the sealed two-phase cooling structure (902a,902b,902c) (see paragraphs [0036], [0038] and fig. 12 of Shen). In re claim 10, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the packaged integrated circuit device further comprising a second semiconductor die 821, wherein the sealed two-phase cooling structure is thermally coupled to the second semiconductor die 821, and wherein the mold compound 807 encapsulates the second semiconductor die 821 (see paragraph [0037] and fig. 11B of Shen). In re claim 11, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the packaged integrated circuit device further comprising a second sealed two-phase cooling structure 36j thermally coupled to the semiconductor die 32, wherein the mold compound 68 encapsulates the second sealed two-phase cooling structure 36j (see paragraph [0075], [0080] and figs. 17 and 21 of Tsai). In re claim 12, as applied to claim 11 above, Tsai in combination with Shen discloses wherein the packaged integrated circuit device further the sealed two-phase cooling structure includes a vapor chamber 36j (see paragraph [0075] and fig. 17 of Tsai) and the second sealed two-phase cooling structure includes one or more heat pipes 4 (see paragraph [0068] and fig. 17 of Tsai). In re claim 13, as applied to claim 1 above, Tsai in combination with Shen discloses wherein the packaged integrated circuit device further comprising a second semiconductor die 821; and a second sealed two-phase cooling structure thermally coupled to the second semiconductor die 821, wherein the mold compound 807 encapsulates the second semiconductor die 821 and the second sealed two-phase cooling structure (see paragraph [0037] and fig. 11B of Shen). In re claim 14, as applied to claim 13 above, Tsai in combination with Shen discloses wherein the sealed two-phase cooling structure includes a vapor chamber 36j (see paragraph [0075] and fig. 17 of Tsai) and the second sealed two-phase cooling structure includes one or more heat pipes 4 (see paragraph [0068] and fig. 17 of Tsai). In re claim 15, Tsai discloses a device comprising a packaged integrated circuit device comprising a semiconductor die 32 (see paragraph [0073] and fig. 21); a sealed cooling structure 4m thermally coupled to the semiconductor die 32 (via thermal adhesive material 34) (see paragraph [0073] and fig. 21); and a mold compound 68 encapsulating the semiconductor die 32 and the sealed cooling structure 4m (see paragraph [0080] and fig. 21); and a printed circuit board (PCB) 2 electrically connected to the packaged integrated circuit device (via leads 62 and bonding wires 66) (see paragraphs [0079], [0080] and fig. 21). Tsai is silent to wherein the sealed cooling structure is a sealed two-phase cooling structure. However, Shen discloses in a same field of endeavor, a packaged integrated circuit device including, inter-alia, a semiconductor die 805 (see paragraph [0036] and fig. 12); a sealed two-phase cooling structure (902a,902b,902c) thermally coupled to the semiconductor die 805 (see paragraph [0038] and fig. 12); and a mold compound 807 encapsulating the semiconductor die 805 (see paragraphs [0036], [0037] and fig. 12), and a printed circuit board (PCB) 806 electrically connected to the packaged integrated circuit device (see paragraph [0036] and fig. 12). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shen into the packaged integrated circuit device of Tsai in order to replace the sealed cooling structure in the packaged integrated circuit device of Tsai with the sealed two-phase cooling structure of Shen in order to directly dissipate heat from the semiconductor die to the upper part through a phase change manner and furthermore a vapor chamber that is adopted to quickly dissipate heat from the heat dissipating object to the outside of the vapor chamber can be obtain (see paragraph [0001] of Shen). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 16, as applied to claim 15 above, Tsai in combination with Shen discloses wherein the packaged integrated circuit device further comprises an interface layer 34 (thermal adhesive material) between the sealed two-phase cooling structure and 4m the semiconductor die 32 (see paragraph [0073] and fig. 21 of Tsai). In re claim 17, as applied to claim 16 above, Tsai in combination with Shen discloses wherein the interface layer 34 includes an adhesive (see paragraph [0073] and fig. 21 of Tsai). In re claim 18, as applied to claim 15 above, Tsai in combination with Shen discloses wherein the sealed two-phase cooling structure (902a,902b,902c) includes a vapor chamber (see paragraph [0038] and fig. 12 of Shen). In re claim 19, Tsai discloses a method of fabricating a packaged integrated circuit device, the method comprising thermally coupling a sealed cooling structure 4m to a semiconductor die 4 (see paragraphs [0073], [0080] and fig. 21); and using a mold compound 68 to encapsulate the sealed cooling structure 4m and the semiconductor die 32 (see paragraph [0068] and fig. 21). Tsai is silent to wherein thermally coupling the sealed cooling structure including thermally coupling a sealed two-phase cooling structure. However, Shen discloses in a same field of endeavor, a method of fabricating a packaged integrated circuit device including, inter-alia, thermally coupling a sealed two-phase cooling structure (902a,902b,902c) to a semiconductor die 805 (see paragraph [0038] and fig. 12); and using a mold compound 807 to encapsulate the semiconductor die 805 (see paragraphs [0036], [0037] and fig. 12). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Shen into the method of fabricating a packaged integrated circuit device of Tsai in order to replace the sealed cooling structure in the packaged integrated circuit device of Tsai with the sealed two-phase cooling structure of Shen so as to enable thermally coupling a sealed two-phase cooling structure to the semiconductor die in Tsai to be performed in order to directly dissipate heat from the semiconductor die to the upper part through a phase change manner and furthermore a vapor chamber that is adopted to quickly dissipate heat from the heat dissipating object to the outside of the vapor chamber can be obtain (see paragraph [0001] of Shen). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 20, as applied to claim 19 above, Tsai in combination with Shen discloses wherein thermally coupling the sealed two-phase cooling structure to the semiconductor die includes applying an interface layer 34 on the semiconductor die 32; and placing the sealed two-phase cooling structure on the interface layer 32, wherein the mold compound 68 encapsulates the interface layer 34 (see paragraphs [0073], [0080] and fig. 21 of Tsai). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bao et al. (U.S. Pub. 2013/0285233) discloses a packaged integrated circuit device including, inter-alia, a semiconductor die 302; a cooling structure 318 thermally coupled to the semiconductor die 302; and a mold compound 324 encapsulating the semiconductor die 302 and the cooling structure 318 (see paragraph [0046] and fig. 3). Lin et al. (U.S. Pub. 2015/0179617) discloses a packaged integrated circuit device including inter-alia, a semiconductor die 20 (see paragraph [0023] and fig. 1); a cooling structure 60 thermally coupled to the semiconductor die 20 (see paragraph [0024] and fig. 1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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Prosecution Timeline

Jul 09, 2024
Application Filed
Sep 24, 2025
Response after Non-Final Action
Jul 14, 2026
Non-Final Rejection mailed — §103
Aug 27, 2026
Examiner Interview Summary
Aug 27, 2026
Applicant Interview (Telephonic)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 4m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 2248 resolved cases by this examiner. Grant probability derived from career allowance rate.

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