Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 17-19 are objected to because of the following informalities:
In claims 17-19, “the first pseudo-inverter circuit” and “the second pseudo-inverter circuit” lack antecedent basis. Replace them with –the first driver circuit— and –the second driver circuit--.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 3 and 16, the recitation “Iac1 is current induced by the parasitic capacitance” is unclear, because according to the specification, Iac1 is current induced by the parasitic capacitance and by the device under test (see [0019]).
In claims 3 and 16, the recitation “Iac2 is current induced by the device under test” is unclear, because according to the specification, Iac2 should be current induced by the parasitic capacitance, Cpar1. (see [0020]).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (U. S. Pub. 2012/0084033).
As for claim 7, Liu et al. discloses a system (see Figs. 1 and 2) comprising:
a first pseudo-inverter circuit (transistor pairs including CP0 and CN0) configure to receive a first voltage (Vdd) and perform only two measurement steps, wherein:
during a first measurement step, a first current (Ivdd0, Ivdd1), induced by a capacitance of a device under test (Cdut) and a parasitic capacitance (Cpar0, Cpar1), is measured (see the measurement step in [0012]—[0013]); and
during a second measurement step, a second current (Ivdd2), induced by the parasitic capacitances (Cpar0 and Cpar1), is measured, and wherein the capacitance of the device under test (Cdut) is characterized by the first current, the second current, and the first voltage (see [0015], [0016]).
As for claim 8, Liu et al. discloses the system of claim 7, wherein the device under test (Cdut) is coupled between the first pseudo-inverter circuit and a second pseudo-inverter circuit;
wherein, during the first measurement step, first control signals (set of control signals from the control circuit) applied to the first pseudo-inverter circuit (the transistors CP0, CN0) and the second pseudo-inverter circuit (transistors CP1 and CN1) facilitate characterization of the first current (Ivdd0 and/or Ivdd1); and
wherein, during the second measurement step, second control signals (second set of control signals from the control circuit) applied to the first pseudo-inverter circuit (the transistors CP0, CN0) and the second pseudo-inverter circuit (the transistors CP1, CN1) facilitate characterization of the second current (Ivdd2).
As for claim 9, Liu et al. discloses the system of claim 7, wherein the device under test (Cdut) is coupled between the first pseudo-inverter circuit (the transistors CP0, CN0) and a second pseudo-inverter circuit(the transistors CP1, CN1), wherein each of the first pseudo-inverter circuit and the second pseudo-inverter circuit is configured to be controlled (using the control circuit) with a plurality of control signals (set of control signals from the control circuit) that are independent input signals.
As for claim 10, Liu et al. discloses the system of claim 7, wherein the device under test (Cdut) is coupled between the first pseudo-inverter circuit (the transistors CP0, CN0) and a second pseudo-inverter circuit(transistor pairs including CP1 and CN1), wherein the first pseudo-inverter circuit is coupled to a first power supply (Vdd), the second pseudo-inverter circuit (transistor pairs including CP1 and CN1) is coupled to a second power supply (DN), the first power supply is configured to generate the first voltage, and the second power supply is configured to generate a second voltage.
As for claim 11, Liu et al. discloses the system of claim 7, wherein the device under test (Cdut) is coupled between the first pseudo-inverter circuit and the second pseudo-inverter circuit, the first voltage (logic low signal) is applied to a first transistor (CP0) of the first pseudo-inverter circuit (transistor pairs including CP0 and CN0), a second voltage (logic high signal) is applied to a second transistor (CP1) of the second pseudo-inverter circuit (transistor pairs including CP1 and CN1), a third transistor (CN0) is coupled between the first transistor (CP0) and a ground, a fourth transistor (CN1) is coupled between the second transistor (CP1) and the ground, the first and third transistors (CP0 and CN0) are coupled together in series, and the second and fourth transistors (Cp1 and CN1) are coupled
together in series (see [0012] and Figs. 1 and 2).
As for claim 12, Liu et al. discloses the system of claim 7, wherein the first pseudo-inverter circuit (transistor pairs including CP0 and CN0) is coupled to a first power supply (Vdd) and the second pseudo-inverter circuit (transistor pairs including CP1 and CN1) is coupled to a second power supply (DN).
As for claim 13, Liu et al. discloses a system (see Figs. 1 and 2) for charge-based capacitor (Cdut) measurement, the system comprising:
a first driver circuit (transistor pairs including CP0 and CN0);
a second driver circuit (transistor pairs including CP1 and CN1); and
a control circuit (control circuit) coupled between the first driver circuit and the second driver circuit, the control circuit configured to generate independent and non-overlapping control signals for the first driver circuit and the second driver circuit;
wherein a device under test (Cdut) is coupled to each of the first driver circuit and the second
driver circuit.
As for claim 14, Liu et al. discloses the system of claim 13, wherein the first driver circuit comprises a first pair of transistors (transistor pairs including CP0 and CN0) and the second driver circuit comprises a second pair of transistors (transistor pairs including CP1 and CN1).
As for claim 15, Liu et al. discloses the system of claim 13, wherein during a first time, the non-overlapping control signals facilitate characterization of a capacitance of the device under test (Cdut) and a parasitic capacitance (Cpar0) and wherein during a second time, the non-overlapping control signals facilitate characterization of the capacitance of the device under test (Cdut is calculated see [0012]—[0016]).
As for claim 17, Liu et al. discloses the system of claim 13, wherein the first driver circuit (transistor pairs including CP0 and CN0) is controlled with a first control signal (first set of control signals from the control circuit to the transistors CP0, CN0), the second driver circuit (transistor pairs including CP1 and CN1)is controlled with a second control signal (second set of control signals from the control circuit to the transistors CP1 and CN1), and the first control signal and the second control signal are non-overlapping, independent input signals.
As for claim 18, Liu et al. discloses the system of claim 13, wherein the first driver circuit (transistor pairs including CP0 and CN0) is coupled to a first power supply (Vdd) and the second driver circuit (transistor pairs including CP1 and CN1) is coupled to a second power supply (DN), and wherein
the first power supply (Vdd) and the second power supply (DN) are different from one another.
As for claim 19, Liu et al. discloses the system of claim 13, wherein the first driver circuit comprises a first pair of transistors (transistors CP0 and CN0) coupled together in series and the second driver circuit comprises a second pair of transistors (transistor pairs including CP1 and CN1) coupled together in series.
As for claim 20, Liu et al. discloses the system of claim 13, wherein the control circuit comprises a signal generating having a tunable timing margin for generating the non-overlapping control signals (using the control circuit in Figs 1 and 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U. S. Pub. 2012/.0084033).
As for claim 16, Liu et al. discloses the system of claim 14, as discussed above, wherein the capacitance of the device under test is expressed as follow:
Cdut=(Ivdd0+Ivdd1)-Ivdd2/ 2*Vdd*f (see Eq. 4 and Eq. 5 in [0015] and [0016] in Liu).
Where Cdut is the capacitance of the device under test, (Ivdd0+Ivdd1) is the sum of the current induced by the parasitic capacitances (Cpar0) and the device under test, and the current induced by the parasitic capacitance (Cpar1) and the device under test (Cdut); Ivdd2 is the current induced by the parasitic capacitances (Cpar0 and Cpar1), Vdd is supply voltage, and f is a clock frequency.
Still referring to claim 16, Liu et al. does not specifically disclose that the device under test is expressed as claimed, using only two current measurement steps.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to further modify Liu et al. to reduce the three current measurement steps to the two current measurement steps to calculate the capacitance of the Cdut, for the purpose of simplifying the calculation of the Cdut when the effect of only one of the parasitic capacitances (e.g., Cpar0) is used for Ivdd2 (i.e., the Cdut=(Ivdd0-Ivdd2)/Vdd*f, where Ivdd0 is the current induced by the parasitic capacitance Cpar0 and the device under test; and Ivdd2 is the current induced by the parasitic capacitance Cpar0).
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U. S. Pub. 2012/.0084033) in view of Yeo et al. (U. S. Pub. 2017/0323134).
As for claim 1, Liu et al. discloses a system (see Figs. 1 and 2) for charge-based capacitor (Cdut1—Cdutn) measurement, the system comprising:
a first pseudo-inverter circuit (transistor pairs including CP0 and CN0) and a second pseudo-inverter circuit (transistor pairs including CP1 and CN1);
a control circuit (see the control circuit in Figs. 1 and 2) coupled between the first pseudo-inverter circuit and the second pseudo-inverter circuit, the control circuit configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit; and
wherein a device under test (Cdut; Cdut1—Cdutn) is coupled to each of the first pseudo-inverter circuit and the second pseudo-inverter circuit.
Still referring to claim 1, Liu et al. does not specifically disclose a shielding metal coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit, the shielding metal configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit.
Yeo et al. discloses a charge transfer circuit for capacitive sensing wherein a conventional shielding metal (see 500 in Fig 8; and [0100]—0102]) is used to reduce noise and avoid parasitic effects.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Liu et al. to couple to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit, a shielding metal, as taught by Yeo et al., for the purpose of noise reduction and avoiding parasitic effect (see [0100]—[0102]).
As for claim 2, Liu et al. in view of Yeo et al. discloses the system of claim 1, wherein during a first time, the non-overlapping control signals facilitate characterization of a capacitance of the device under test (Cdut) and a parasitic capacitance (Cpar0 and/or Cpar1) and wherein during a second time, the non-overlapping control signals facilitate characterization of the capacitance of the device under test (Cdut is calculated see [0012]—[0016].
As for claim 3, Liu et al. in view of Yeo et al. discloses the system of claim 2, as discussed above, wherein the capacitance of the device under test is expressed as follow:
Cdut=(Ivdd0+Ivdd1)-Ivdd2/ 2*Vdd*f (see Eq. 4 and Eq. 5 in [0015] and [0016] in Liu).
Where Cdut is the capacitance of the device under test, (Ivdd0+Ivdd1) is the sum of the current induced by the parasitic capacitances (Cpar0) and the device under test, and the current induced by the parasitic capacitance (Cpar1) and the device under test (Cdut); Ivdd2 is the current induced by the parasitic capacitances (Cpar0 and Cpar1), Vdd is supply voltage, and f is a clock frequency.
Still referring to claim 3, Liu et al. in view of Yeo et al. does not specifically disclose that the device under test is expressed as claimed, using only two current measurement steps.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to further modify Liu et al. to reduce the three current measurement steps to the two current measurement steps to calculate the capacitance of the Cdut, for the purpose of simplifying the calculation of the Cdut when the effect of only one of the parasitic capacitances (e.g., Cpar0) is used for Ivdd2 (i.e., the Cdut=(Ivdd0-Ivdd2)/Vdd*f, where Ivdd0 is the current induced by the parasitic capacitance Cpar0 and the device under test; and Ivdd2 is the current induced by the parasitic capacitance Cpar0).
As for claim 4, Liu et al. in view of Yeo et al. discloses the system of claim 1, wherein the first pseudo-inverter circuit (transistor pairs including CP0 and CN0) is controlled with a first control signal (using control circuit), the second pseudo-inverter circuit (transistor pairs including CP1 and CN1) is controlled with a second control signal (using control circuit), and the first control signal and the second control signal are non-overlapping, independent input signals.
As for claim 5, Liu et al. in view of Yeo et al. discloses the system of claim 1, wherein the first pseudo-inverter circuit (transistor pairs including CP0 and CN0) is coupled to a first power supply (Vdd) and the second pseudo-inverter circuit (transistor pairs including CP1 and CN1) is coupled to a second power supply (DN), and wherein the first power supply and the second power supply are different from one another (see Fig. 2).
As for claim 6, Liu et al. in view of Yeo et al. discloses the system of claim 1, wherein the first pseudo-inverter circuit comprises a first pair of transistors (transistor pairs including CP0 and CN0) coupled together in series and the second pseudo-inverter circuit comprises a second pair of transistors (transistor pairs including CP1 and CN1) coupled together in series.
Conclusion
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/AMY HE/Primary Examiner, Art Unit 2858