DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7-8 and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki (JP 2008205402 A).
As to Claim 1, Suzuki discloses:
A computing system (electronic module, see Figs. 1-3) comprising:
a main board (motherboard 12); and
sub-board units (memory units 14a,14b) connected to the main board 12 (Par. 0026 “memory units 14A and 14B are mounted on both ends of the motherboard 12”),
wherein each sub-board unit 14a,14b comprises:
a first sub-board (substrate 28 of 14a) electrically connected to the main board 12 and comprising first chips 30 arranged on a side of the first sub-board 28 (see Fig. below);
a second sub-board (28 of 14b) electrically connected to the main board 12 and comprising second chips 30 arranged on a side of the second sub-board (see Fig. below); and
a cooling structure (heat dissipation member 34 of Fig. 7) sandwiched between the first sub-board (28 of 14a) and the second sub-board (28 of 14b; see Fig. below, 34 sandwiched between highlighted first and second sub-boards 28),
wherein the first sub-board 28 and the second sub-board 28 are arranged such that the side of the first sub-board and side of the second sub-board both face the cooling structure (sides of boards 28 face 34), and
wherein a first region of the first sub-board defined by an outline of a first chip (highlighted chip 30), among the first chips, wherein the first region is directly opposite an identical second region of the second sub-board (28 of 14b), and wherein at least a portion of a second chip (highlighted chip 30 of 14b), among the second chips, that corresponds to the first chip, is outside the second region (highlighted chip 30 of 14b, corresponding to highlighted first chip 30 of 14a is outside of second region).
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As to Claim 7, Suzuki discloses:
wherein the first chips and the second chips are respectively disposed on the first sub-board and the second sub-board to form a same chip layout pattern (both chips 30 of board 28 of 14a,14b are disposed in same layout).
As to Claim 8, Suzuki discloses:
wherein the chip layout pattern is a grid pattern (chips 30 are disposed in a grid pattern, see Figs. 1-3).
As to Claim 11, Suzuki discloses:
wherein
the first chips are arranged to form first chip groups (two first chips 30 of highlighted Fig. in rejection of claim 1 above), each first chip group having at least two first chips disposed adjacently (chips are adjacent), and
the second chips is arranged to form second chip groups (two second chips 30 in Fig. above), each second chip group having at least two second chips disposed adjacently (second chips 30 are adjacent).
As to Claim 12, Suzuki discloses:
wherein at least a partial region of a second chip group is arranged not to overlap with a corresponding first chip group as viewed from a direction perpendicular to the sides of the first and second sub-boards (see Fig. in rejection of claim 1 above, chip 30 on right side of second chip group does not overlap with first chip group).
As to Claim 13, Suzuki discloses:
wherein the first sub-board and the second sub-board (first and second boards highlighted in rejection of claim 1 above) are configured to share the cooling structure 34 (34 cools both first and second boards), wherein tops of the first chips 30 face the cooling structure 34, and wherein tops of the second chips 30 also face the cooling structure 34 (both the outside faces of the chips, e.g., tops, face 34).
As to Claim 14, Suzuki discloses:
wherein the cooling structure 34 is in contact with the tops of the first chips 30 and with the tops of the second chips 30 to cool the first chips and the second chips (34 is in both physical and thermal contact with outside faces of highlighted first and second chips 30).
As to Claim 15, Suzuki discloses:
wherein the cooling structure 34 comprises a flow path for a liquid or gaseous cooling fluid to flow (34 comprises fins 38, space between fins provides flow path for airflow) or a heat exchange member for heat exchange.
As to Claim 16, Suzuki discloses:
An electronic device (electronic module, see Figs. 1-3) comprising:
a main board (motherboard 12); and
sub-board units (memory units 14a,14b) connected to the main board 12 (Par. 0026 “memory units 14A and 14B are mounted on both ends of the motherboard 12”),
each sub-board unit 14a,14b comprising:
a cooling structure (heat dissipation member 34 of Fig. 7) disposed between a first sub-board (substrate 28 of 14a) and a second sub-board (28 of 14b; 28 of 14b; see Fig. below, 34 sandwiched between highlighted first and second sub-boards 28);
the first sub-board (28 of 14a) electrically connected to the main board 12 and comprising first chips 30 arranged on a surface of the first sub-board that faces the cooling structure 34 and that faces the second sub-board (28 of 14b; see Fig. below);
the second sub-board (28 of 14b) electrically connected to the main board 12 and comprising second chips 30 disposed on a surface of the second sub-board that faces the cooling structure 34 and that faces the first sub-board (28 of 14a; see Fig. below; first and second boards 28 electrically connected to 12 via connectors 26 and boards 16); and
wherein the first sub-board and the second sub-board 28 are arranged such that tops of the first chips 30 and tops of the second chips 30 face the cooling structure 34 (both the outside faces of the chips, e.g., tops, face 34), and
wherein, from a direction perpendicular to the first and second sub-boards 28, at least a partial region a second chip among the second chips does not overlap with any of the first chips (see Fig. below, highlighted second chip does not overlap with any first chip 30).
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As to Claim 17, Suzuki discloses:
wherein, from the direction perpendicular to the first and second sub-boards the second chips (see highlighted second chips 30 in Fig. in rejection of claim 16 above) respectively correspond, positionally, to the first chips (first chips 30; first and second chips correspond, both situated within 10), and each second chip has at least a portion thereof that does not overlap its corresponding first chip (rightmost second chip corresponds to right most first chip, and leftmost second chips corresponds to leftmost first chip; neither corresponding chip overlaps).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (JP 2008205402 A) as applied to claim 16 above, and further in view of Tan (US 20210321543 A1).
As to Claim 20, Suzuki does not disclose:
wherein the electronic device is a supercomputer or a server.
However, Tan discloses:
wherein the electronic device is a supercomputer or a server (Par. 0078 “Embodiments herein may be implemented in various types of computing… racks, and blade servers such as those employed in a data center and/or server farm environment”);
in order to provide adaptability to various types of computing and networking equipment (Par. 0078).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Suzuki as further suggested by Tan e.g., providing:
wherein the electronic device is a supercomputer or a server;
in order to provide adaptability to various types of computing and networking equipment.
Allowable Subject Matter
Claims 2-6, 9-10 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claims 2-6, 9-10 and 18-19, the allowability resides in the overall structure and functionality of the device as recited in the dependent claims 2, 4-6, 9 and 18-19, including all of the limitations of their base claims and intervening claims, and at least in part, because claims 2, 4-6, 9 and 18-19 recite the following limitations:
“wherein the first chips are arranged on the first sub-board in a first layout having a chip layout pattern, wherein the second chips are arranged with a second layout also having the chip layout pattern, and wherein the first layout has an offset along a dimension of the first sub-board that differs from an offset of the second layout along the dimension of the second sub-board.” – claim 2;
“wherein a layout of the second chips is offset with respect to the same layout of the first chips in a first direction and in a second direction that is perpendicular to the first direction, the first sub-board and the second sub-board being aligned across from each other in the sub-board unit.” – claim 4;
“wherein each of the first chips and the second chips have a same chip area, wherein each first chip only partially overlaps, from a perspective perpendicular to the sides of the first and second sub-boards, a respectively corresponding second chip, and wherein such overlaps have an area less than or equal to one half of the chip area.” – claim 5;
“wherein, from a perspective perpendicular to the sides of the first and second sub-boards, the none of the second chips are overlapped by any of the first chips.” – claim 6;
“wherein, viewed from a direction perpendicular to the sides of the first and second sub-boards, each of the second chips overlaps a respectively corresponding first chip and also overlaps with non-chip space on the first sub-board.” – claim 9;
“wherein the first chips and the second chips each have the same area, and wherein the area of each of regions where the first chips and the second chips only partially overlap with each other is less than or equal to one half of the area of each of the first and second chips.” – claim 18;
“wherein
the first chips and the second chips are respectively arranged on the first sub-board and the second sub-board with a same grid pattern, and
from the direction perpendicular to the sides of the first and second sub-boards, each of the second chips overlaps with at least some space of the first sub-board that does not contain any of the first chips.” – claim 19.
Kim (US 20200034327 A1) discloses a memory module with a plurality of components, but does not disclose the claimed configuration of chips.
Franz (US 11785743 B2) discloses a cooling structure for memory board, but does not disclose the claimed configuration of chips.
Patel (US 6496375 B2) discloses a high-density packaging assembly for electronics with a cooling structure, but does not disclose the claimed configuration of chips.
Wei (US 7933125 B2) discloses a board unit with a cooling structure, but does not disclose the claimed configuration of chips.
The aforementioned limitations in combination with all remaining limitations of claims 2, 4-6, 9 and 18-19, are believed to render said claims 2, 4-6, 9 and 18-19 and all claims dependent therefrom allowable over the prior art of record, taken alone or in combination.
Further, Examiner has not identified any double patenting issues.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW S MUIR whose telephone number is (571)270-1329. The examiner can normally be reached Monday - Friday 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW SINCLAIR MUIR/ Examiner, Art Unit 2841
/Jayprakash N Gandhi/ Supervisory Patent Examiner, Art Unit 2841
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