DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 2 and 4 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kweon et al. (US Pub. 2023/0096678; hereinafter “Kweon”).
Regarding Claim 1, Kweon discloses a semiconductor chip comprising: a semiconductor substrate 100 (page 4, paragraph 54); a bonding layer 220 (page 5, paragraph 61) above an upper surface 110BS of the semiconductor substrate 100 (see figs. 11 and 13), the bonding layer 220 comprising a bonding pad 222 and a bonding insulating layer 221 (pages 4-5, paragraph 57) surrounding at least a portion of a side surface of the bonding pad 222 (see figs. 11 and 13); and a circuit layer 230 (page 5, paragraph 61) between the semiconductor substrate 100 and the bonding layer 220 (the circuit layer 230 of semiconductor chip 200A is between an upper bonding layer 220 and the substrate 100; see fig. 13), the circuit layer 230 comprising a circuit insulating layer 231 and an electric line 232 in the circuit insulating layer 231 (page 4, paragraph 56; page 5, paragraph 61; see figs. 11 and 13), wherein a horizontal width of the circuit layer 230 is less than a horizontal width of the semiconductor substrate 100 (see figs. 11 and 13), and wherein a sidewall of the semiconductor substrate 100 is spaced apart from a sidewall of the circuit layer 230 in a horizontal direction (X-direction) (see figs. 11 and 13).
Regarding Claim 2, Kweon discloses wherein an upper edge surface of the semiconductor substrate 100 is spaced apart from the circuit layer 230 in the horizontal direction (X-direction) (see figs. 11 and 13), and wherein the upper edge surface of the semiconductor substrate 100 is exposed (the upper edge surface of the semiconductor substrate 100 is exposed from the circuit layer 230; see figs. 11 and 13).
Regarding Claim 4, Kwon discloses wherein the sidewall of the circuit layer 230, an upper edge surface of the semiconductor substrate 100, and the sidewall of the semiconductor substrate 100 form a stepped structure (see figs. 11 and 13).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yao et al. (US Pub. 2024/0063178; hereinafter “Yao”).
Regarding Claim 1, Yao discloses a semiconductor chip comprising: a semiconductor substrate 118; a bonding layer 106 (interconnect; page 7, paragraph 81) above an upper surface of the semiconductor substrate 118 (see fig. 1A), the bonding layer 106 comprising a bonding pad 132 and a bonding insulating layer 109 (page 7, paragraph 81) surrounding at least a portion of a side surface of the bonding pad 132 (see figs. 1A and 1B); and a circuit layer 116 (metallization stack; page 7, paragraph 79) between the semiconductor substrate 118 and the bonding layer 106 (see fig. 1A), the circuit layer 116 comprising a circuit insulating layer (insulator) and an electric line (conductive traces) in the circuit insulating layer (page 7, paragraph 79), wherein a horizontal width of the circuit layer 116 is less than a horizontal width of the semiconductor substrate 118 (see fig. 1A), and wherein a sidewall of the semiconductor substrate 118 is spaced apart from a sidewall of the circuit layer 116 in a horizontal direction (y-axis) (see fig. 1A).
Regarding Claim 2, Yao discloses wherein an upper edge surface of the semiconductor substrate 118 is spaced apart from the circuit layer 116 in the horizontal direction (y-axis) (see fig. 1A), and wherein the upper edge surface of the semiconductor substrate 118 is exposed (the upper edge surface of the substrate 118 is exposed from the circuit layer 116; see fig. 1A).
Regarding Claim 4, Yao discloses wherein the sidewall of the circuit layer 116, an upper edge surface of the semiconductor substrate 118, and the sidewall of the semiconductor substrate 118 form a stepped structure (see fig. 1A).
Allowable Subject Matter
Claims 3 and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 recites an angle formed between the sidewall of the semiconductor substrate and the upper edge surface of the semiconductor substrate is greater than about 90 degrees and less than about 120 degrees.
Claim 5 recites an angle formed between the upper surface of the semiconductor substrate and the sidewall of the circuit layer is at least about 60 degrees and less than about 90 degrees.
Claim 6 recites the circuit layer further comprises a connection pad connected to the electric line, and wherein the connection pad contacts the bonding pad.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claim 7 depends from claim 6, so it is objected for the same reason.
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 8 recites a second bonding layer below the second semiconductor substrate; a second circuit layer between the second semiconductor substrate and the second bonding layer, and wherein a horizontal width of the second circuit layer is less than a horizontal width of the second semiconductor substrate.
Claim 14 recites each of the plurality of scribe lane regions comprises an inspection region and trench regions on both sides of the inspection region; forming a second mask layer filling a space corresponding to the removed portion of the bonding insulating layer and the removed portion of the circuit insulating layer; removing at least a portion the second mask layer, the bonding layer, and the circuit layer from the inspection region by performing a second laser grooving process; removing the semiconductor substrate from the inspection region by performing a second plasma process; and removing the second mask layer from at least one region other than the inspection region.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 9-13 and 15-20 variously depend from claim 8 or 14, so they are allowed for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 July 25, 2026
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