DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 112 3
A. Claims 9, 12, 16, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 3
III. Claim Rejections - 35 USC § 102 5
A. Claims 1-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0125230 (“Lu”). 5
IV. Claim Rejections - 35 USC § 103 8
A. Claims 11-13, 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of US 2018/0020550 (“Jang”). 9
B. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Jang, as applied to claim 11 above, and further in view of US 2022/0028777 (Kim”). 15
V. Allowable Subject Matter 16
VI. Pertinent Prior Art 18
Conclusion 18
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 9, 12, 16, and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 reads,
9. The COF package of claim 1, wherein the plurality of input pads entirely and vertically overlap the plurality of bridge patterns
The word “overlap” is defined as “to extend over or past and cover a part of” (emphasis added; Merriam-Webster Dictionary: https://www.merriam-webster.com/dictionary/overlap). Thus, the term “entirely” in the context of “entirely and vertically overlap” is a contradiction in terms and renders the claim indefinite.
In addition, give the orientation of the input pads and the bridge patterns shown in the drawings, i.e. Figs. 2A-2D and 3A-3C, while the input pads are positioned vertically over the bridge patterns, there is no part of the input pad and the bridge pattern, that “vertically overlap”, a term suggesting that there are portions of each of the input pad and its corresponding bridge pattern have portions overlapping in the Z direction of Figs. 2A-2D and 3A-3C, i.e. in the thickness direction. Rather, the overlap is in the X-Y plane, particularly bearing in mind that each of the input pads and the bridge patterns extend in the “second horizontal direction”, i.e. the Y direction.
To the extent that Applicant is intending to claim that which is shown in, e.g., Figs. 2D or 3C of the Instant Application, then Applicant may use terminology such as an “an entirety of each of the plurality of input pads overlaps a corresponding bridge pattern of the plurality of bridge patterns”.
Claim 12 reads,
12. The COF package of claim 11, wherein a portion of each of the plurality of first bridge patterns vertically overlaps a corresponding input pad of the plurality of input pads.
As explained above, there is no vertical overlap between the input pads and the corresponding bridge patterns. As such, the claim is indefinite.
Claim 16 reads,
16. The COF package of claim 11, further comprising: a stiffener on a lower surface of the base film, wherein the lower surface of the base film is opposite the upper surface of the base film, and the stiffener vertically overlaps the semiconductor chip.
For similar reasons to those explained under claim 9, Fig. 5 of the Instant Application shows that the stiffener 20 and the semiconductor chip 10 are vertically oriented to each other, but the overlap between them is in the X-Y plane. As such, the claim is unclear because there is no part of the stiffener and the semiconductor chip that “vertically overlap”.
Claim 20 reads in pertinent part,
20. The COF package of claim 17, wherein … the plurality of input pads vertically overlap the plurality of bridge patterns, respectively.
See discussion under claims 9 and 12, which applies equally here.
For the purposes of patentability, the claims will be read as broadly as allowed by the current claim language.
III. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0125230 (“Lu”).
With regard to claim 1, Lu discloses, generally in Figs. 11, 12, 19, 20, 58, and 59,
1. A chip on film (COF) package comprising:
[1] a base film [lower “substrate layer 101” in Figs. 12, 58, 59 (¶¶ 113-114)] including a first side [FOF in Figs. 19-20 (¶ 160)] extending in a first horizontal direction [horizontally in Fig. 20; X in Figs. 11, 12, 58, 59];
[2] a plurality of conductive lines 104B [¶¶ 117, 180] on an upper surface of the base film [lower “substrate layer 101”] and extending in a second horizontal direction [vertically in Fig. 20; Y in Fig. 11; into/out of plane of page in Figs. 12, 58, 59], the second horizontal direction being perpendicular to the first horizontal direction;
[3] a plurality of bridge patterns 104B [¶ 180] respectively connected with the plurality of conductive lines 104B and arranged along the first side of the base film;
[4] an interlayer insulation layer [upper “substrate layer 101” in Figs. 12, 58, 59 (¶ 186; Figs. 51 to 52)] on the base film [lower “substrate layer 101”] and covering a plurality of bridge patterns 104B; and
[5] a plurality of input pads [102 in bonding region FOF in Figs. 19, 20 (¶¶ 113, 115-116)] on the interlayer insulation layer [upper “substrate layer 101”] and respectively connected with the plurality of bridge patterns 104B [by means of the vias, i.e. “second transfer electrodes 106” (¶¶ 186-189) as shown in Figs. 11, 12, 58, 59].
With regard to features [2] and [3] of claim 1 and claim 6,
6. The COF package of claim 1, wherein each of the plurality of bridge patterns 104B is a portion of a corresponding conductive line 104B of the plurality of conductive lines 104B.
As consistent with claim 6, the conductive lines and the bridge patterns are one and the same, as required by claim 6.
This is all of the limitations of claims 1 and 6.
With regard to claims 2-5 and 7,-9, Lu further discloses,
2. The COF package of claim 1, wherein
[1] the plurality of conductive lines 104B are at a first vertical level, and
[2] the plurality of input pads 102 are at a second vertical level, and
[3] the second vertical level is higher than the first vertical level [as shown in Figs. 12, 58, 59].
3. The COF package of claim 1, wherein the plurality of input pads 102 have an island shape on the interlayer insulation layer [upper “substrate layer 101”] [as shown in Figs. 11-12, 58, 59].
4. The COF package of claim 1, wherein the plurality of input pads 102 are arranged in zigzag in the first horizontal direction [as shown in Fig. 11].
5. The COF package of claim 1, wherein
[1] the plurality of input pads comprise a plurality of first input pads [102 at the lowermost side of Fig. 11] and a plurality of second input pads [102 at the uppermost side of Fig. 11],
[2] the plurality of first input pads [102 at the lowermost side of Fig. 11] are adjacent to the first side [lowermost side in Fig. 11] of the base film [lower substrate layer 101 in Fig. 12],
[3] the plurality of second input pads [102 at the uppermost side of Fig. 11] are farther away from the first side of the base film [lower substrate layer 101 in Fig. 12] in the second horizontal direction Y than the plurality of first input pads [102 at the lowermost side of Fig. 11], and
[4] the plurality of first input pads [102 at the lowermost side of Fig. 11] and the plurality of second input pads [102 at the uppermost side of Fig. 11] are arranged in parallel in the first horizontal direction X [to every extent that the input pads are “arranged in parallel” in the Instant Application given that they are “arranged in zigzag” as recited in claim 4 and shown in the drawings in the Instant Application].
7. The COF package of claim 1, wherein
[1] the plurality of bridge patterns 104B extend in parallel in the second horizontal direction Y,
[2] end portions of the plurality of bridge patterns 104B face the first side [FOF in Figs. 19-20] of the base film [lower “substrate layer 101” in Figs. 12, 58, 59], and
[3] the end portions of the plurality of bridge patterns 104B are arranged in parallel in the first horizontal direction X [as shown in Fig. 11].
8. The COF package of claim 1, wherein
[1] the plurality of bridge patterns 104B extend in parallel in the second horizontal direction Y, and
[2] lengths of some of the plurality of bridge patterns 104B in the second horizontal direction Y differ from lengths of others of the plurality of bridge patterns 104B in the second horizontal direction Y [as shown in Fig. 11].
9. The COF package of claim 1, wherein the plurality of input pads 102 entirely and vertically overlap the plurality of bridge patterns 104B.
Bearing in mind the rejection under 35 USC 112(b), above, Lu discloses this feature to every extent that it is disclosed in the Instant Application, which is not at all.
With regard to claim 10, Lu further discloses,
10. The COF package of claim 1, further comprising:
[1] a plurality of connection vias 106 passing through the interlayer insulation layer [upper “substrate layer 101”] in a vertical direction Z,
wherein
[2] the plurality of connection vias 106 respectively contact the plurality of bridge patterns 104B at 1042' and the plurality of input pads 102 [as shown in Figs. 11, 12, and 58], and
[3] the plurality of connection vias 106 are arranged in zigzag in the first horizontal direction X [as shown in Fig. 11].
IV. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 11-13, 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of US 2018/0020550 (“Jang”).
Claim 11 reads,
11. A chip on film (COF) package comprising:
[1] a base film including a first bonding region, a second bonding region, and a circuit region between the first bonding region and the second bonding region;
[2] a plurality of conductive lines on an upper surface of the base film in the circuit region;
[3] a protection layer covering the plurality of conductive lines on the upper surface of the base film;
[4a] a semiconductor chip on the upper surface of the base film in the circuit region,
[4b] the semiconductor chip connected with one end of a first group of conductive lines among the plurality of conductive lines;
[5a] a plurality of first bridge patterns on the upper surface of the base film in the first bonding region,
[5b] the plurality of first bridge patterns arranged in parallel in a first horizontal direction and connected with an other end of the first group of conductive lines;
[6] a first interlayer insulation layer covering the plurality of first bridge patterns on the upper surface of the base film in the first bonding region; and
[7] a plurality of input pads on the first interlayer insulation layer and arranged in zigzag in the first horizontal direction, and
[8] the plurality of input pads respectively being connected with the plurality of first bridge patterns.
With regard to claim 11, Lu discloses, generally in Figs. 11, 12, 19, 20, 58, and 59,
11. A chip on film (COF) package comprising:
[1] a base film [lower “substrate layer 101” in Figs. 12, 58, 59 (¶¶ 113-114)] including a first bonding region FOF, a second bonding region OLB, and a circuit region [IC or generally at ILB] between the first bonding region FOF and the second bonding region OLB [Figs. 19-20; ¶¶ 132, 160];
[2] a plurality of conductive lines 104B on an upper surface of the base film [lower “substrate layer 101”] in the circuit region [IC or generally at ILB];
[3] a protection layer 111 [¶¶ 132, 160] covering the plurality of conductive lines 104 on the upper surface of the base film [lower “substrate layer 101”];
[4a] a semiconductor chip IC [¶¶ 132, 160, 196; Fig. 20] on the upper surface of the base film [lower “substrate layer 101”] in the circuit region [IC or generally at ILB],
[4b] the semiconductor chip IC connected with one end of a first group of conductive lines 104B among the plurality of conductive lines 104B;
[5a] a plurality of first bridge patterns 104B on the upper surface of the base film [lower “substrate layer 101”] in the first bonding region FOF,
[5b] the plurality of first bridge patterns 104B arranged in parallel in a first horizontal direction X and connected with an other end of the first group of conductive lines 104B;
[6] a first interlayer insulation layer [upper “substrate layer 101” in Figs. 12, 58, 59 (¶ 186; Figs. 51 to 52)] covering the plurality of first bridge patterns 104B on the upper surface of the base film [lower “substrate layer 101”] in the first bonding region FOF; and
[7] a plurality of input pads 102 on the first interlayer insulation layer [upper “substrate layer 101”] and arranged in zigzag in the first horizontal direction X [as shown in Fig. 11], and
[8] the plurality of input pads 102 respectively being connected with the plurality of first bridge patterns 104 [as shown in Figs. 11 and 12].
With regard to feature [4b] of claim 11,
[4b] the semiconductor chip connected with one end of a first group of conductive lines among the plurality of conductive lines;
Inasmuch as Lu discloses a chip-on-film package [title], the conductive lines 104B for input and for output are necessarily, inherently connected the IC chip shown in Figs. 19 and 20. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Nonetheless Lu does not show or anywhere state that the IC chip is “connected with one end of a first group of conductive lines among the plurality of conductive lines”. So it is not entirely clear that “one end” of a conductive line 104B is connected to the IC chip in Figs. 19 and 20.
Jang, like Lu, teaches a chip-on-film package for a display having input pads 260 and output pads 270 at respective ends of the base film 210 with a circuit region therebetween where the integrated circuit chip 220 is mounted (Jang: Figs. 5, 11; ¶ 75-76; title). Each of Figs. 5 and 11 of Jang further teach that one end of a first group of conductive input lines 230 extending from the input pads 260, i.e. the groups that include pads IVP and IHP (Jang: ¶¶ 78-79), to connect to the integrated circuit chip 220, as well as a second group of output lines 240 connected to output pads 270 that are bonded to the input pads of the display panel (Jang: ¶¶ 76-83).
Jang also includes a third group of conductive lines 235, i.e. a “a plurality of connecting wirings 235” (Jang: ¶ 76) extending directly from of input pads 260 to the output pads 270, bypassing the integrated circuit chip 220. These are relevant to independent claim 17 (infra).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have (1) the input bridge pattern/conductive lines 104B of Lu extend from the input pads 102 (in region FOF) to the circuit region ILB to have one end electrically connect with the integrated circuit chip IC and (2) the output bridge pattern/conductive lines 104B of Lu extend from the output pads 102 (in region OLB) to the circuit region ILB to have one end electrically connect with the integrated circuit chip IC because Jang teaches that this is a known configuration for the wiring lines in a chip-on-film package.
This is all of the limitations of claim 11.
With regard to claims 12 and 13, Lu further discloses,
12. The COF package of claim 11, wherein a portion of each of the plurality of first bridge patterns 104B vertically overlaps a corresponding input pad 102 of the plurality of input pads 102 [as shown in Figs. 12, 58, 59].
13. The COF package of claim 11, wherein the plurality of input pads 102 have an island shape on the first interlayer insulation layer [upper “substrate layer 101”].
With regard to claim 15, Lu modified according to Jang as explained under claim 11, further teaches,
15. The COF package of claim 11, further comprising:
[1] a plurality of second bridge patterns 104B on the upper surface of the base film [lower “substrate layer 101”] in the second bonding region OLB and arranged in parallel in the first horizontal direction X [Lu: Figs. 19-20];
[2] a second interlayer insulation layer [upper “substrate layer 101”] covering the plurality of second bridge patterns 104B on the upper surface of the base film [lower “substrate layer 101”]; and
[3a] a plurality of output pads 102 on the second interlayer insulation layer [upper “substrate layer 101”] and arranged in zigzag in the first horizontal direction [as shown in Fig. 11],
[3b] the plurality of output pads 102 respectively being connected with the plurality of second bridge patterns 104B.
Claim 17 reads,
17. A chip on film (COF) package comprising:
[1] a base film including a first bonding region, a second bonding region, and a circuit region between the first bonding region and the second bonding region;
[2] a semiconductor chip on the base film in the circuit region;
[3] a plurality of bridge patterns on the base film in the first bonding region;
[4] a plurality of output pads on the base film in the second bonding region;
[5a] a plurality of conductive lines on the base film in the circuit region, the plurality of conductive lines including
[5b] a plurality of input lines respectively connecting the semiconductor chip with the plurality of bridge patterns,
[5c] a plurality of output lines respectively connecting the semiconductor chip with the plurality of output pads, and
[5d] a plurality of bypass lines respectively connecting the plurality of bridge patterns with the plurality of output pads;
[6] a protection layer on the base film and covering the plurality of conductive lines in the circuit region;
[7] an interlayer insulation layer on the base film and covering the plurality of bridge patterns in the first bonding region; and
[8] a plurality of input pads on the interlayer insulation layer and respectively connected with the plurality of bridge patterns.
With regard to claim 17, Lu discloses, generally in Figs. 11, 12, 19, 20, 58, and 59,
17. A chip on film (COF) package comprising:
[1] a base film [lower “substrate layer 101” in Figs. 12, 58, 59 (¶¶ 113-114)] including a first bonding region FOF, a second bonding region OLB, and a circuit region [IC or generally at ILB] between the first bonding region FOF and the second bonding region OLB [Figs. 19-20; ¶¶ 132, 160];
[2] a semiconductor chip IC [¶¶ 132, 160, 196; Fig. 20] on the base film [lower “substrate layer 101”] in the circuit region ILB;
[3] a plurality of bridge patterns 104B on the base film [lower “substrate layer 101”] in the first bonding region FOF [Figs. 11, 19, 20];
[4] a plurality of output pads 102 on the base film [lower “substrate layer 101”] in the second bonding region OLB;
[5a] a plurality of conductive lines 104B on the base film [lower “substrate layer 101”] in the circuit region ILC, the plurality of conductive lines 104B including
[5b] a plurality of input lines respectively connecting the semiconductor chip with the plurality of bridge patterns,
[5c] a plurality of output lines respectively connecting the semiconductor chip with the plurality of output pads, and
[5d] a plurality of bypass lines respectively connecting the plurality of bridge patterns with the plurality of output pads;
[6] a protection layer 111 on the base film [lower “substrate layer 101”] and covering the plurality of conductive lines 104B in the circuit region;
[7] an interlayer insulation layer [upper “substrate layer 101” in Figs. 12, 58, 59 (¶ 186; Figs. 51 to 52)] on the base film [lower “substrate layer 101”] and covering the plurality of bridge patterns in the first bonding region FOF; and
[8] a plurality of input pads 102 on the interlayer insulation layer [upper “substrate layer 101”] and respectively connected with the plurality of bridge patterns 104B.
With regard to features [5a] to [5d], as explained under claim 11 above, Lu does not show the ends of the input and output bridge patterns/conductive lines 104B connected to the integrated circuit chip IC and also does not teach the claimed “bypass lines”.
In addition to being obvious to include each of the pluralities of input and output lines 104B in Lu connected to the integrated circuit chip IC, as taught in Jang, for the reasons explained under claim 11 above, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, in addition, to include the bypass lines 235 of Jang “respectively connecting the plurality of bridge patterns [104B of Lu] with the plurality of output pads [102 in OLB region of Lu]”, i.e. bypassing the integrated circuit chip, in order to provide connections directly from the input pads to the output pads allowing direct communication between an input device and the display panel, as taught in Jang. As such, Jang may be seen as an improvement to Lu, in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 17.
With regard to claim 20, Lu further discloses,
20. The COF package of claim 17, wherein
[1] the plurality of bridge patterns 104B are arranged in parallel in a first horizontal direction X,
[2] the plurality of input pads 102 are arranged in zigzag in the first horizontal direction X [as shown in Fig. 11], and
[3] the plurality of input pads 102 vertically overlap the plurality of bridge patterns 104B, respectively [as shown in Figs. 11, 12, 58, and 59].
B. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Jang, as applied to claim 11 above, and further in view of US 2022/0028777 (Kim”).
Claim 16 reads,
16. The COF package of claim 11, further comprising:
[1] a stiffener on a lower surface of the base film,
[2] wherein the lower surface of the base film is opposite the upper surface of the base film, and the stiffener vertically overlaps the semiconductor chip.
The prior art of Lu in view of Jang, as explained above, teaches each of the features of claim 11.
Neither Lu nor Jang teaches a stiffener.
Kim, like each of Lu and Jang, teaches a COF package (Kim: Figs. 1-3; title). Kim further includes a heat radiator 160 on the surface of the base film 110 opposite to the surface on which the integrated circuit chip 100 is mounted (Kim: ¶¶ 55-57; Figs. 4-10). The heat radiator may be made of Cu, Al or W (Kim: ¶ 57). Paragraph [0105] of the Instant Application states that metals such as Cu can be used as the stiffener 20. As such, it is held that at least the heat radiator 160 of Kim is inherently capable of functioning as a stiffener, as evidenced by the Instant Application. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the heat radiator 160 and associated structures, 150, dam structure DS, 155, and 170, on the back surface of the base film 101 of Lu, directly opposed to the integrated circuit chip IC, in order to aid heat dissipation from the integrated circuit chip, as taught in Kim. As such, Kim may be seen as an improvement to Lu in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 16.
V. Allowable Subject Matter
Claims 14, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 reads,
14. The COF package of claim 11, further comprising:
[1] a plurality of output pads on the upper surface of the base film in the second bonding region,
[2] the protection layer exposing the plurality of output pads by not covering the plurality of output pads,
wherein
[3] the plurality of output pads are connected with the semiconductor chip through a second group of conductive lines among the plurality of conductive lines, and
[4] the plurality of output pads are at a same vertical level as the plurality of first bridge patterns.
With regard to claim 14, Lu modified according to Jang as explained under claim 11, further teaches,
14. The COF package of claim 11, further comprising:
[1] a plurality of output pads 102 on the upper surface of the base film [lower “substrate layer 101”] in the second bonding region OLB [Figs. 19-20 of Lu],
[2] the protection layer 111 exposing the plurality of output pads 102 by not covering the plurality of output pads 102 [as shown in Figs. 19 and 20 of Lu],
wherein
[3] the plurality of output pads 102 are connected with the semiconductor chip IC through a second group of conductive lines 104B among the plurality of conductive lines 104B [as taught by Jang, above], and
[4] … [not taught] …
The prior art does not reasonably teach or suggest—in the context of claim 14—the
[4] the plurality of output pads are at a same vertical level as the plurality of first bridge patterns.
Claim 18 reads,
18. The COF package of claim 17, wherein the plurality of output pads, the plurality of conductive lines, and the plurality of bridge patterns are at a first vertical level.
As with claim 14, the prior art does not reasonably teach or suggest—in the context of claim 18—that “the plurality of output pads, the plurality of conductive lines, and the plurality of bridge patterns are at a first vertical level”.
Claim 19 is allowed at least for including the same allowable limitations by depending from claim 18.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN-116110914-A (“Li”) is cited for disclosing at least all of the limitations of claim 1. See Figs. 2, 3, and especially Figs. 6-9, and the associated text in the attached machine language translation.
US 2019/0287888 (“Koo”) is cited for disclosing all of the limitations of claim 1 except for the positioning of the circuit region between the input and output pad regions. Instead, the circuit region and the output pad region are at the sides of the base film while the input pad region is between them. See Figs. 6, 7, and 8 and the associated text.
US 2019/0385936 (“Pun”) is cited for making a multi-level metal substrate specifically for a COF package. See Figs. 7A-7Q and 8 and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
