DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements filed on 06/27/2025, 07/10/2024, 11/25/2025 and 03/06/2026 have been considered.
Drawings
The drawings filed on 07/09/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 07/09/2024 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Suh (US 2020/0381427).
Regarding claims 1 and 9, Suh discloses:
An integrated circuit structure, comprising:
a semiconductor island (114, ¶0027) on a semiconductor substrate (102, ¶0014); and
a nanowire (N2, ¶0036) above a fin (FA, ¶0036), the fin protruding from the semiconductor substrate (102), wherein a channel region of the nanowire is electrically isolated from the fin (¶0057), and wherein the semiconductor island (114) has an uppermost surface above an uppermost surface of the nanowire (N1).
Regarding claims 2 and 10, Suh further discloses:
a second nanowire (N3, ¶0036) above the nanowire (N1).
Regarding claims 3 and 11, Suh further discloses:
a second nanowire (N1) below the nanowire.
Regarding claims 4 and 12, Suh further discloses:
wherein the semiconductor island(114) and the nanowire (N2) comprise a same semiconductor material (silicon, ¶0014, ¶0022, ¶0025).
Regarding claim 5 and 13, Suh further discloses:
a gate stack (150, ¶0054) over the nanowire (N2).
Regarding claims 6 and 14, Suh further discloses:
a first epitaxial source or drain structure (160, ¶0060) at a first end of the nanowire; and
a second epitaxial source or drain structure (160) at a second end of the nanowire, the second end laterally opposite the first end.
Regarding claims 7 and 15, Suh further discloses:
a first conductive contact (192) on the first epitaxial source or drain structure;
a second conductive contact (192) on the second epitaxial source or drain structure; and
a third conductive contact (194) on the semiconductor island (¶0062).
Regarding claims 8 and 16, Suh further discloses:
wherein the second fin (FA) is electrically coupled to the semiconductor island (114).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Guha (US 2021/0184014).
Regarding claim 17, Guha (US 2021/0184014) discloses:
A computing device (900, ¶0131), comprising:
a board (902, ¶0131); and
a component (904, ¶0131) coupled to the board (902) the component including an integrated circuit structure, comprising:
a semiconductor island (220, ¶0032) on a semiconductor substrate; and
a nanowire (206 (¶0032) above a fin (204, ¶0032), the fin protruding from the semiconductor substrate (202), wherein a channel region of the nanowire (206) is electrically isolated (with dielectric 214, ¶0032) from the fin (204), and wherein the semiconductor island (220) has an uppermost surface above an uppermost surface of the nanowire (206).
Regarding claim 18, Guha further discloses:
a memory (¶0132) coupled to the board (902).
Regarding claim 19, Guha further discloses:
a communication chip (906, ¶0133) coupled to the board (902)
Regarding claim 20, Guha further discloses:
wherein the component is a packaged integrated circuit die (¶0134).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
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